diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v
index 642406c3..a0dcb099 100644
--- a/verilog/rtl/digital_pll.v
+++ b/verilog/rtl/digital_pll.v
@@ -76,7 +76,7 @@ module digital_pll(
         .VPWR(VPWR),
         .VGND(VGND),
         .VPB(VPWR),
-        .VNB(vssd),
+        .VNB(VGND),
 `endif
         .A(clockp_buffer_in[0]),
         .X(clockp[0])