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Added spare logic blocks for GPIO (#153) 

* Added enough spare logic blocks to have the existing four above
the processor, plus one each per GPIO (38 for caravel, 27 for
caravan).

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
This commit is contained in:
R. Timothy Edwards 2022-10-07 04:24:01 -04:00 committed by GitHub
parent be25ae7476
commit cfbe353290
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 30 additions and 22 deletions
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4
manifest
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@ -2,10 +2,10 @@
87735eb5981740ca4d4b48e6b0321c8bb0023800 verilog/rtl/__uprj_netlists.v
684085713662e37a26f9f981d35be7c6c7ff6e9a verilog/rtl/__user_analog_project_wrapper.v
b5ad3558a91e508fad154b91565c7d664b247020 verilog/rtl/__user_project_wrapper.v
24ed502194cb86e86abf9d94aa0d0918bf8556c9 verilog/rtl/caravan.v
40fa6c17c38634a72759f07d16fe9b5f55e36d45 verilog/rtl/caravan.v
1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d verilog/rtl/caravan_netlists.v
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
c6851e521ea59a923437c3b3efca8ceb225f1d54 verilog/rtl/caravel.v
cee8e7bdd3e904c6665d32ea92f56540f5718ac9 verilog/rtl/caravel.v
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
fdddad12354f0aaf93b9df98980e8a28fb59df65 verilog/rtl/chip_io.v

24
verilog/rtl/caravan.v
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@ -1411,17 +1411,21 @@ module caravan (
.X(rstb_l)
);
// Spare logic for metal mask fixes
wire [107:0] spare_xz_nc;
wire [15:0] spare_xi_nc;
wire [3:0] spare_xib_nc;
wire [7:0] spare_xna_nc;
wire [7:0] spare_xno_nc;
wire [7:0] spare_xmx_nc;
wire [7:0] spare_xfq_nc;
wire [7:0] spare_xfqn_nc;
/* Spare logic for metal mask fixes */
`define NUM_SPARE_BLOCKS (`MPRJ_DIG_PADS+4)
spare_logic_block spare_logic [3:0] (
wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
// Four spare logic blocks above the processor and one per GPIO
// control block.
spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),

24
verilog/rtl/caravel.v
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@ -1463,17 +1463,21 @@ module caravel (
.X(rstb_l)
);
// Spare logic for metal mask fixes
wire [107:0] spare_xz_nc;
wire [15:0] spare_xi_nc;
wire [3:0] spare_xib_nc;
wire [7:0] spare_xna_nc;
wire [7:0] spare_xno_nc;
wire [7:0] spare_xmx_nc;
wire [7:0] spare_xfq_nc;
wire [7:0] spare_xfqn_nc;
/* Spare logic for metal mask fixes */
`define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4)
spare_logic_block spare_logic [3:0] (
wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
// Four spare logic blocks above the processor and one per GPIO
// control block.
spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
`ifdef USE_POWER_PINS
.vccd(vccd_core),
.vssd(vssd_core),