diff --git a/manifest b/manifest
index 9cdd7f90..7de3a29b 100644
--- a/manifest
+++ b/manifest
@@ -2,10 +2,10 @@
 87735eb5981740ca4d4b48e6b0321c8bb0023800  verilog/rtl/__uprj_netlists.v
 684085713662e37a26f9f981d35be7c6c7ff6e9a  verilog/rtl/__user_analog_project_wrapper.v
 b5ad3558a91e508fad154b91565c7d664b247020  verilog/rtl/__user_project_wrapper.v
-24ed502194cb86e86abf9d94aa0d0918bf8556c9  verilog/rtl/caravan.v
+40fa6c17c38634a72759f07d16fe9b5f55e36d45  verilog/rtl/caravan.v
 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d  verilog/rtl/caravan_netlists.v
 a3d12a2d2d3596800bec47d1266dce2399a2fcc6  verilog/rtl/caravan_openframe.v
-c6851e521ea59a923437c3b3efca8ceb225f1d54  verilog/rtl/caravel.v
+cee8e7bdd3e904c6665d32ea92f56540f5718ac9  verilog/rtl/caravel.v
 2fe34f043edbe87c626e5616ad54f82c9ba067c2  verilog/rtl/caravel_clocking.v
 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650  verilog/rtl/caravel_openframe.v
 fdddad12354f0aaf93b9df98980e8a28fb59df65  verilog/rtl/chip_io.v
diff --git a/verilog/rtl/caravan.v b/verilog/rtl/caravan.v
index 935aeac6..747c8eb7 100644
--- a/verilog/rtl/caravan.v
+++ b/verilog/rtl/caravan.v
@@ -1411,17 +1411,21 @@ module caravan (
 		.X(rstb_l)
     );
 
-    // Spare logic for metal mask fixes
-    wire [107:0] spare_xz_nc;
-    wire [15:0] spare_xi_nc;
-    wire [3:0] spare_xib_nc;
-    wire [7:0] spare_xna_nc;
-    wire [7:0] spare_xno_nc;
-    wire [7:0] spare_xmx_nc;
-    wire [7:0] spare_xfq_nc;
-    wire [7:0] spare_xfqn_nc;
+    /* Spare logic for metal mask fixes */
+    `define NUM_SPARE_BLOCKS (`MPRJ_DIG_PADS+4)
 
-    spare_logic_block spare_logic [3:0] (
+    wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
+    wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
+    wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
+
+    // Four spare logic blocks above the processor and one per GPIO
+    // control block.
+    spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
 	`ifdef USE_POWER_PINS
 		.vccd(vccd_core),
 		.vssd(vssd_core),
diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v
index 1aca6bdc..b5fd8c58 100644
--- a/verilog/rtl/caravel.v
+++ b/verilog/rtl/caravel.v
@@ -1463,17 +1463,21 @@ module caravel (
 		.X(rstb_l)
     );
 
-    // Spare logic for metal mask fixes
-    wire [107:0] spare_xz_nc;
-    wire [15:0] spare_xi_nc;
-    wire [3:0] spare_xib_nc;
-    wire [7:0] spare_xna_nc;
-    wire [7:0] spare_xno_nc;
-    wire [7:0] spare_xmx_nc;
-    wire [7:0] spare_xfq_nc;
-    wire [7:0] spare_xfqn_nc;
+    /* Spare logic for metal mask fixes */
+    `define NUM_SPARE_BLOCKS (`MPRJ_IO_PADS+4)
 
-    spare_logic_block spare_logic [3:0] (
+    wire [(27*`NUM_SPARE_BLOCKS)-1:0] spare_xz_nc;
+    wire [(4*`NUM_SPARE_BLOCKS)-1:0] spare_xi_nc;
+    wire [(1*`NUM_SPARE_BLOCKS)-1:0] spare_xib_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xna_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xno_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xmx_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfq_nc;
+    wire [(2*`NUM_SPARE_BLOCKS)-1:0] spare_xfqn_nc;
+
+    // Four spare logic blocks above the processor and one per GPIO
+    // control block.
+    spare_logic_block spare_logic [`NUM_SPARE_BLOCKS-1:0] (
 	`ifdef USE_POWER_PINS
 		.vccd(vccd_core),
 		.vssd(vssd_core),