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fix power pins assignment of clockp buffers

This commit is contained in:
kareem 2022-10-13 11:00:04 -07:00
parent 59743f4832
commit fdf1f11ece
1 changed files with 7 additions and 7 deletions
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14
verilog/rtl/digital_pll.v
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@ -73,9 +73,9 @@ module digital_pll(
(* keep *)
sky130_fd_sc_hd__clkbuf_16 clockp_buffer_0 (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPWR),
.VNB(vssd),
`endif
.A(clockp_buffer_in[0]),
@ -85,10 +85,10 @@ module digital_pll(
(* keep *)
sky130_fd_sc_hd__clkbuf_16 clockp_buffer_1 (
`ifdef USE_POWER_PINS
.VPWR(vccd),
.VGND(vssd),
.VPB(vccd),
.VNB(vssd),
.VPWR(VPWR),
.VGND(VGND),
.VPB(VPWR),
.VNB(VGND),
`endif
.A(clockp_buffer_in[1]),
.X(clockp[1])