From fdf1f11ecebfa018c11f6a1d5c7543badd4b7d2b Mon Sep 17 00:00:00 2001 From: kareem Date: Thu, 13 Oct 2022 11:00:04 -0700 Subject: [PATCH] fix power pins assignment of clockp buffers --- verilog/rtl/digital_pll.v | 14 +++++++------- 1 file changed, 7 insertions(+), 7 deletions(-) diff --git a/verilog/rtl/digital_pll.v b/verilog/rtl/digital_pll.v index 2f18f041..642406c3 100644 --- a/verilog/rtl/digital_pll.v +++ b/verilog/rtl/digital_pll.v @@ -73,9 +73,9 @@ module digital_pll( (* keep *) sky130_fd_sc_hd__clkbuf_16 clockp_buffer_0 ( `ifdef USE_POWER_PINS - .VPWR(vccd), - .VGND(vssd), - .VPB(vccd), + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), .VNB(vssd), `endif .A(clockp_buffer_in[0]), @@ -85,10 +85,10 @@ module digital_pll( (* keep *) sky130_fd_sc_hd__clkbuf_16 clockp_buffer_1 ( `ifdef USE_POWER_PINS - .VPWR(vccd), - .VGND(vssd), - .VPB(vccd), - .VNB(vssd), + .VPWR(VPWR), + .VGND(VGND), + .VPB(VPWR), + .VNB(VGND), `endif .A(clockp_buffer_in[1]), .X(clockp[1])