add test la test

verilog/dv/cocotb/caravel_tests.py

@@ -40,7 +40,7 @@ from tests.mgmt_gpio.mgmt_gpio import *
 from tests.timer.timer import *
 from tests.uart.uart import *
 from tests.spi_master.spi_master import *
-
+from tests.logicAnalyzer.la import *
 
 
 

verilog/dv/cocotb/tests.json

@@ -240,5 +240,12 @@
             "GL":["r_gl","nightly","weekly","tape_out"],
             "GL_SDF":["r_sdf","weekly","tape_out"],
             "description":"check Housekeeping SPI disable register is working"}
+
+        ,"la" :{"level":0, 
+            "SW":true,
+            "RTL":["r_rtl","setup","nightly","weekly","tape_out"],
+            "GL":["r_gl","nightly","weekly","tape_out"],
+            "GL_SDF":["r_sdf","weekly","tape_out"],
+            "description":"check logic analyzer input and output enable"}
     }
 }

verilog/dv/cocotb/tests/logicAnalyzer/.vscode/c_cpp_properties.json

@@ -0,0 +1,16 @@
+{
+    "configurations": [
+        {
+            "name": "Linux",
+            "includePath": [
+                "${workspaceFolder}/**"
+            ],
+            "defines": [],
+            "compilerPath": "/usr/bin/gcc",
+            "cStandard": "gnu17",
+            "cppStandard": "gnu++14",
+            "intelliSenseMode": "linux-gcc-x64"
+        }
+    ],
+    "version": 4
+}

verilog/dv/cocotb/tests/logicAnalyzer/la.c

@@ -0,0 +1,111 @@
+
+#include <defs.h>
+#include <stub.c>
+
+void main(){
+    unsigned int i, j, k;
+    reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
+    reg_debug_1  = 0x0;
+    reg_debug_2  = 0x0;
+    reg_hkspi_disable = 1;
+
+    // Configure LA probes [63:32] and [127:96] as inputs to the cpu 
+	// Configure LA probes [31:0] and [63:32] as outputs from the cpu
+    reg_la0_oenb = reg_la0_iena = 0xFFFFFFFF;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0x00000000;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0xFFFFFFFF;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0x00000000;    // [127:96]
+
+    reg_la0_data = 0xAAAAAAAA;
+    reg_la2_data = 0xAAAAAAAA;
+
+    reg_debug_2 = reg_la1_data_in;
+    if (reg_la1_data_in != 0xAAAAAAAA)
+        reg_debug_1 = 0x1E;
+    else 
+        reg_debug_1 = 0x1B;
+    reg_debug_2 = reg_la3_data_in;
+    if (reg_la3_data_in != 0xAAAAAAAA)
+        reg_debug_1 = 0x2E;
+    else 
+        reg_debug_1 = 0x2B;    
+
+    reg_la0_data = 0x55555555;
+    reg_la2_data = 0x55555555;
+
+    reg_debug_2 = reg_la1_data_in;
+    if (reg_la1_data_in != 0x55555555)
+        reg_debug_1 = 0x3E;
+    else 
+        reg_debug_1 = 0x3B;
+ 
+    reg_debug_2 = reg_la3_data_in;
+    if (reg_la3_data_in != 0x55555555)
+        reg_debug_1 = 0x4E;
+    else 
+        reg_debug_1 = 0x4B;    
+
+    // Configure LA probes [31:0] and [63:32] as inputs to the cpu 
+	// Configure LA probes [63:32] and [127:96] as outputs from the cpu
+    reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
+    reg_la1_data = 0xAAAAAAAA;
+    reg_la3_data = 0xAAAAAAAA;
+
+    reg_debug_2 = reg_la0_data_in;
+    if (reg_la0_data_in != 0xAAAAAAAA)
+        reg_debug_1 = 0x5E;
+    else 
+        reg_debug_1 = 0x5B;
+
+    reg_debug_2 = reg_la2_data_in;
+    if (reg_la2_data_in != 0xAAAAAAAA)
+        reg_debug_1 = 0x6E;
+    else 
+        reg_debug_1 = 0x6B;    
+
+    reg_la1_data = 0x55555555;
+    reg_la3_data = 0x55555555;
+
+    reg_debug_2 = reg_la0_data_in;
+    if (reg_la0_data_in != 0x55555555)
+        reg_debug_1 = 0x7E;
+    else 
+        reg_debug_1 = 0x7B;
+ 
+    reg_debug_2 = reg_la2_data_in;
+    if (reg_la2_data_in != 0x55555555)
+        reg_debug_1 = 0x8E;
+    else 
+        reg_debug_1 = 0x8B;    
+
+    // Configure LA probes [31:0] and [63:32] as inputs to the cpu 
+	// Configure LA probes [63:32] and [127:96] as disabled input and output
+    reg_la0_oenb = reg_la0_iena = 0x00000000;    // [31:0]
+	reg_la1_oenb = reg_la1_iena = 0xFFFFFFFF;    // [63:32]
+	reg_la2_oenb = reg_la2_iena = 0x00000000;    // [95:64]
+	reg_la3_oenb = reg_la3_iena = 0xFFFFFFFF;    // [127:96]
+
+    reg_la1_iena = reg_la3_iena = 0x00000000; // disable input for la1 and la3
+
+    reg_la1_data = 0xAAAAAAAA;
+    reg_la3_data = 0xAAAAAAAA;
+
+    reg_debug_2 = reg_la0_data_in;
+    if (reg_la0_data == 0xAAAAAAAA)
+        reg_debug_1 = 0x9E;
+    else 
+        reg_debug_1 = 0x9B;
+ 
+    reg_debug_2 = reg_la2_data_in;
+    if (reg_la2_data == 0xAAAAAAAA)
+        reg_debug_1 = 0xaE;
+    else 
+        reg_debug_1 = 0xaB;    
+
+    reg_debug_2 = 0xFF;
+    
+}

verilog/dv/cocotb/tests/logicAnalyzer/la.py

@@ -0,0 +1,48 @@
+import random
+import cocotb
+from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
+import cocotb.log
+from cpu import RiskV
+from defsParser import Regs
+from cocotb.result import TestSuccess
+from tests.common_functions.test_functions import *
+from tests.bitbang.bitbang_functions import *
+from caravel import GPIO_MODE
+from cocotb.binary import BinaryValue
+
+reg = Regs()
+
+@cocotb.test()
+@repot_test
+async def la(dut):
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
+    cpu = RiskV(dut)
+    cpu.cpu_force_reset()
+    cpu.cpu_release_reset()
+    pass_list = (0x1B,0x2B,0x3B,0x4B,0x5B,0x6B,0x7B,0x8B,0x9B,0xaB)
+    fail_list = (0x1E,0x2E,0x3E,0x4E,0x5E,0x6E,0x7E,0x8E,0x9E,0xaE)
+    phases_fails = 10
+    phases_passes = 0
+    reg1 =0 # buffer
+    while True: 
+        if cpu.read_debug_reg2() == 0xFF:  # test finish 
+            break
+        if reg1 != cpu.read_debug_reg1():
+            reg1 = cpu.read_debug_reg1()                
+            if reg1 in pass_list:  # pass phase
+                phases_passes +=1
+                phases_fails  -=1
+                cocotb.log.info(f"[TEST] test passes phase {hex(reg1)[2]}")   
+            elif reg1 in fail_list:  # fail phase
+                cocotb.log.error(f"[TEST] test fails phase {hex(reg1)[2]} incorrect value recieved {hex(cpu.read_debug_reg2())}")   
+           
+        await ClockCycles(caravelEnv.clk,1) 
+
+    if phases_fails != 0:
+        cocotb.log.error(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails") 
+    else:
+        cocotb.log.info(f"[TEST] finish with {phases_passes} phases passes and {phases_fails} phases fails")    
+
+    await ClockCycles(caravelEnv.clk, 10000)
+
+   

verilog/dv/cocotb/verify_cocotb.py

@@ -80,7 +80,9 @@ class RunTest:
     def runTest_vcs(self):
         print(f"Start running test: {self.sim_type}-{self.test_name}")
         dirs = f'+incdir+\\\"{go_up(self.cocotb_path,4)}\\\" '
-        macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS'
+        macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
+        if self.test_name == "la":
+            macros = f'{macros} +define+LA_TESTING'
         # shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
         # if os.path.exists(f'{self.test_full_dir}/test_data'):
         #     shutil.copyfile(f'{self.test_full_dir}/test_data',f'{self.sim_path}/test_data')

verilog/rtl/__user_project_la_example.v

@@ -0,0 +1,47 @@
+// SPDX-FileCopyrightText: 2020 Efabless Corporation
+//
+// Licensed under the Apache License, Version 2.0 (the "License");
+// you may not use this file except in compliance with the License.
+// You may obtain a copy of the License at
+//
+//      http://www.apache.org/licenses/LICENSE-2.0
+//
+// Unless required by applicable law or agreed to in writing, software
+// distributed under the License is distributed on an "AS IS" BASIS,
+// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+// See the License for the specific language governing permissions and
+// limitations under the License.
+// SPDX-License-Identifier: Apache-2.0
+
+`default_nettype none
+/*
+ *-------------------------------------------------------------
+ *
+ * user_project_la_example
+ *
+ * This is a user project for testing the la only 
+ *
+ *-------------------------------------------------------------
+ */
+
+module user_project_la_example (
+    // Logic Analyzer Signals
+    input  [127:0] la_data_in,
+    output [127:0] la_data_out,
+    input  [127:0] la_oenb
+);
+    // LA
+    assign la_data_out[63:32]  =  la_oenb[31:0]   ?  32'hz: la_data_in[31:0]   ; // assign la0 to la1 if la0 output enable
+    assign la_data_out[31:0]   =  la_oenb[63:32]  ?  32'hz: la_data_in[63:32]   ; // assign la1 to la0 if la1 output enable
+    assign la_data_out[127:96] =  la_oenb[95:64]  ?  32'hz: la_data_in[95:64]   ; // assign la2 to la3 if la2 output enable
+    assign la_data_out[95:64]  =  la_oenb[127:96] ?  32'hz: la_data_in[127:96]  ; // assign la3 to la2 if la3 output enable
+    // // LA
+    // assign la_data_out[63:32]  =  la_oenb[31:0]   ?  la_data_in[31:0]   : 32'hz ; // assign la0 to la1 if la0 output enable
+    // assign la_data_out[31:0]   =  la_oenb[63:32]  ?  la_data_in[63:32]  : 32'hz ; // assign la1 to la0 if la1 output enable
+    // assign la_data_out[127:96] =  la_oenb[95:64]  ?  la_data_in[95:64]  : 32'hz ; // assign la2 to la3 if la2 output enable
+    // assign la_data_out[95:64]  =  la_oenb[127:96] ?  la_data_in[127:96] : 32'hz ; // assign la3 to la2 if la3 output enable
+   
+
+endmodule
+
+`default_nettype wire

verilog/rtl/__user_project_wrapper.v

@@ -87,6 +87,10 @@ assign io_oeb = 0;
 assign io_out = io_in;
 `endif
 
+`ifdef LA_TESTING
+user_project_la_example la_testing(la_data_in,la_data_out,la_oenb);
+`endif
+
 // splitting the address space to user address space and debug address space 
 // debug address space are the last 2 registers of user_project_wrapper address space
 wire wbs_cyc_i_user;