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added power connection to buffer top level rtl

This commit is contained in:
Marwan Abbas 2022-10-15 11:27:30 +02:00
parent e7af9a3aec
commit 6c19140590
1 changed files with 4 additions and 0 deletions
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4
verilog/rtl/caravel.v
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@ -246,6 +246,10 @@ module caravel (
// top-level buffers
buff_flash_clkrst flash_clkrst_buffers (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
.VGND(vssd_core),
`endif
.in_n({
caravel_clk,
caravel_rstn,