From 6c191405905058502a06d9b0971dec3c01467d04 Mon Sep 17 00:00:00 2001 From: Marwan Abbas Date: Sat, 15 Oct 2022 11:27:30 +0200 Subject: [PATCH] added power connection to buffer top level rtl --- verilog/rtl/caravel.v | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/verilog/rtl/caravel.v b/verilog/rtl/caravel.v index 1aa740db..ef76cc1f 100644 --- a/verilog/rtl/caravel.v +++ b/verilog/rtl/caravel.v @@ -246,6 +246,10 @@ module caravel ( // top-level buffers buff_flash_clkrst flash_clkrst_buffers ( + `ifdef USE_POWER_PINS + .VPWR(vccd_core), + .VGND(vssd_core), + `endif .in_n({ caravel_clk, caravel_rstn,