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added power connection to buffer rtl

This commit is contained in:
Marwan Abbas 2022-10-15 12:56:40 +02:00
parent 6c19140590
commit 40c7776b57
1 changed files with 14 additions and 2 deletions
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16
verilog/rtl/buff_flash_clkrst.v
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@ -1,5 +1,17 @@
module buff_flash_clkrst (input[11:0] in_n, input[2:0] in_s, output[11:0] out_s, output[2:0] out_n);
module buff_flash_clkrst (
input[11:0] in_n,
input[2:0] in_s,
output[11:0] out_s,
output[2:0] out_n,
input VPWR,
input VGND);
sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (.A({in_n, in_s}), .X({out_s, out_n}) );
sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (
.A({in_n, in_s}),
.X({out_s, out_n}),
.VGND(VGND),
.VNB(VGND),
.VPB(VPWR),
.VPWR(VPWR));
endmodule