From 40c7776b57f18d253d97342c81d35ed25dcba129 Mon Sep 17 00:00:00 2001 From: Marwan Abbas Date: Sat, 15 Oct 2022 12:56:40 +0200 Subject: [PATCH] added power connection to buffer rtl --- verilog/rtl/buff_flash_clkrst.v | 16 ++++++++++++++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/verilog/rtl/buff_flash_clkrst.v b/verilog/rtl/buff_flash_clkrst.v index eb9b0b1b..08885c64 100644 --- a/verilog/rtl/buff_flash_clkrst.v +++ b/verilog/rtl/buff_flash_clkrst.v @@ -1,5 +1,17 @@ -module buff_flash_clkrst (input[11:0] in_n, input[2:0] in_s, output[11:0] out_s, output[2:0] out_n); +module buff_flash_clkrst ( + input[11:0] in_n, + input[2:0] in_s, + output[11:0] out_s, + output[2:0] out_n, + input VPWR, + input VGND); - sky130_fd_sc_hd__clkbuf_8 BUF[14:0] (.A({in_n, in_s}), .X({out_s, out_n}) ); + sky130_fd_sc_hd__clkbuf_8 BUF[14:0] ( + .A({in_n, in_s}), + .X({out_s, out_n}), + .VGND(VGND), + .VNB(VGND), + .VPB(VPWR), + .VPWR(VPWR)); endmodule \ No newline at end of file