152 add pass thru for clock and reset (#154)

* update caravel.v and caravan.v for clock and reset passthru.

* Apply automatic changes to Manifest and README.rst

* Apply automatic changes to Manifest and README.rst

Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
Co-authored-by: Mohamed Shalan <mshalan@aucegypt.edu>
Co-authored-by: shalan <shalan@users.noreply.github.com>

manifest

@@ -2,10 +2,10 @@
 87735eb5981740ca4d4b48e6b0321c8bb0023800  verilog/rtl/__uprj_netlists.v
 684085713662e37a26f9f981d35be7c6c7ff6e9a  verilog/rtl/__user_analog_project_wrapper.v
 b5ad3558a91e508fad154b91565c7d664b247020  verilog/rtl/__user_project_wrapper.v
-5b92ba15873bfee3ddae89ad7c8f111aec3df187  verilog/rtl/caravan.v
+220d7b7f62f07b3fbe88ea87699bf7cb24336ce5  verilog/rtl/caravan.v
 1b8dc7f0a4f2196b7c2de926af9c648ebf315f3d  verilog/rtl/caravan_netlists.v
 a3d12a2d2d3596800bec47d1266dce2399a2fcc6  verilog/rtl/caravan_openframe.v
-4f5fd35a0b28297ee25e44cf85b7a647edcc6785  verilog/rtl/caravel.v
+2f166c83511062c0366af3f30870aab2ccfe1b25  verilog/rtl/caravel.v
 2fe34f043edbe87c626e5616ad54f82c9ba067c2  verilog/rtl/caravel_clocking.v
 3b9185fd0dc2d0e8c49f1af3d14724e0948fe650  verilog/rtl/caravel_openframe.v
 fdddad12354f0aaf93b9df98980e8a28fb59df65  verilog/rtl/chip_io.v

verilog/rtl/caravan.v

@@ -417,6 +417,10 @@ module caravan (
     // Management processor (wrapper).  Any management core
     // implementation must match this pinout.
 
+    // Pass thru clock and reset
+    wire 	clk_passthru;
+    wire 	resetn_passthru;
+
     mgmt_core_wrapper soc (
 	`ifdef USE_POWER_PINS
 	    .VPWR(vccd_core),
@@ -427,6 +431,12 @@ module caravan (
        	.core_clk(caravel_clk),
        	.core_rstn(caravel_rstn),
 
+    // Pass thru Clock and reset
+	.clk_in(caravel_clk),
+	.resetn_in(caravel_rstn),
+	.clk_out(clk_passthru),
+	.resetn_out(resetn_passthru),
+
 	// GPIO (1 pin)
 	.gpio_out_pad(gpio_out_core),
 	.gpio_in_pad(gpio_in_core),
@@ -527,9 +537,9 @@ module caravan (
 	    .vdda2(vdda2_core),
 	    .vssa2(vssa2_core),
 	`endif
-	.caravel_clk(caravel_clk),
+	.caravel_clk(clk_passthru),
 	.caravel_clk2(caravel_clk2),
-	.caravel_rstn(caravel_rstn),
+	.caravel_rstn(resetn_passthru),
 	.mprj_iena_wb(mprj_iena_wb),
 	.mprj_cyc_o_core(mprj_cyc_o_core),
 	.mprj_stb_o_core(mprj_stb_o_core),

verilog/rtl/caravel.v

@@ -371,6 +371,10 @@ module caravel (
     // Management processor (wrapper).  Any management core
     // implementation must match this pinout.
 
+    // Pass thru clock and reset
+    wire 	clk_passthru;
+    wire 	resetn_passthru;
+
     mgmt_core_wrapper soc (
 	`ifdef USE_POWER_PINS
 	    .VPWR(vccd_core),
@@ -381,6 +385,12 @@ module caravel (
 	.core_clk(caravel_clk),
 	.core_rstn(caravel_rstn),
 
+    // Pass thru Clock and reset
+	.clk_in(caravel_clk),
+	.resetn_in(caravel_rstn),
+	.clk_out(clk_passthru),
+	.resetn_out(resetn_passthru),
+
 	// GPIO (1 pin)
 	.gpio_out_pad(gpio_out_core),
 	.gpio_in_pad(gpio_in_core),
@@ -481,9 +491,9 @@ module caravel (
 	    .vdda2(vdda2_core),
 	    .vssa2(vssa2_core),
 	`endif
-	.caravel_clk(caravel_clk),
+	.caravel_clk(clk_passthru),
 	.caravel_clk2(caravel_clk2),
-	.caravel_rstn(caravel_rstn),
+	.caravel_rstn(resetn_passthru),
 	.mprj_iena_wb(mprj_iena_wb),
 	.mprj_cyc_o_core(mprj_cyc_o_core),
 	.mprj_stb_o_core(mprj_stb_o_core),