mirror of https://github.com/efabless/caravel.git
Add gpio_all_bidir_user test
This commit is contained in:
M0stafaRady
parent
8cca3a5002
commit
7fe790649d
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@ -69,6 +69,12 @@
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"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
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"GL_SDF":["r_sdf","weekly","tape_out"],
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"description":"configure all gpios as mgmt bidir using automatic approach firmware and check them"}
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,"gpio_all_bidir_user" :{"level":0,
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"SW":true,
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"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
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"GL":["r_gl","push_gl","nightly","weekly","tape_out"],
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"GL_SDF":["r_sdf","weekly","tape_out"],
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"description":"configure all gpios as user bidir using automatic approach firmware and check them"}
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,"bitbang_cpu_all_10" :{"level":0,
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"SW":true,
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"RTL":["r_rtl","setup","push","push_gl","nightly","weekly","tape_out"],
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@ -0,0 +1,115 @@
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#include <defs.h>
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#include <stub.c>
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#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
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#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
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#define reg_oeb_userl (*(volatile uint32_t*)0x300FFFEC)
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#define reg_oeb_userh (*(volatile uint32_t*)0x300FFFE8)
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void main(){
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unsigned int i, j, k;
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reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
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reg_debug_1 = 0x0;
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reg_debug_2 = 0x0;
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reg_hkspi_disable = 1;
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reg_mprj_io_37 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_36 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_35 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_34 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_33 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_32 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_31 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_30 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_29 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_28 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_27 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_26 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_25 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_24 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_23 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_22 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_21 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_20 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_19 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_18 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_17 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_16 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_15 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_14 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_13 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_12 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_11 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_10 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_9 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_8 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_7 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_6 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_5 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_4 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_3 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_2 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_1 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_BIDIRECTIONAL;
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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reg_oeb_userl = 0x0;
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reg_oeb_userh = 0x0;
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reg_debug_1 = 0x1A; // try the gpios as output
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reg_mprj_userl = 0x0;
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reg_mprj_userh = 0x0;
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i = 0x20;
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for (j = 0; j < 5; j++) {
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reg_mprj_userh = i;
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reg_debug_2 = 37-j;
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reg_mprj_userh = 0x00000000;
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reg_debug_2 = 0;
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i >>=1;
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i |= 0x20;
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}
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i = 0x80000000;
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for (j = 0; j < 32; j++) {
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reg_mprj_userh = 0x3f;
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reg_mprj_userl = i;
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reg_debug_2 = 32-j;
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reg_mprj_userh = 0x00;
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reg_mprj_userl = 0x00000000;
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reg_debug_2 = 0;
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i >>=1;
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i |= 0x80000000;
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}
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reg_oeb_userl = 0xFFFFFFFF;
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reg_oeb_userh = 0x3F;
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reg_mprj_userl =0;
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reg_mprj_userh =0;
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// test input
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reg_debug_1 = 0XAA; // configuration done wait environment to send 0xFFFFFFFF to reg_mprj_userl
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while (reg_mprj_userl != 0xFFFFFFFF);
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reg_debug_2 = reg_mprj_userl;
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reg_debug_1 = 0XBB; // configuration done wait environment to send 0xAAAAAAAA to reg_mprj_userl
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while (reg_mprj_userl != 0xAAAAAAAA);
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reg_debug_2 = reg_mprj_userl;
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reg_debug_1 = 0XCC; // configuration done wait environment to send 0x55555555 to reg_mprj_userl
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while (reg_mprj_userl != 0x55555555);
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reg_debug_2 = reg_mprj_userl;
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reg_debug_1 = 0XDD; // configuration done wait environment to send 0x0 to reg_mprj_userl
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while (reg_mprj_userl != 0x0);
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reg_debug_2 = reg_mprj_userl;
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reg_debug_1 = 0XD1;
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while (reg_mprj_userh != 0x3F);
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reg_debug_2 = reg_mprj_userh;
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reg_debug_1 = 0XD2;
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while (reg_mprj_userh != 0x0);
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reg_debug_2 = reg_mprj_userh;
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reg_debug_1 = 0XD3;
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while (reg_mprj_userh != 0x15);
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reg_debug_2 = reg_mprj_userh;
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reg_debug_1 = 0XD4;
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while (reg_mprj_userh != 0x2A);
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reg_debug_2 = reg_mprj_userh;
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reg_debug_1 = 0XD5;
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reg_debug_2=0xFF;
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}
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@ -1,7 +1,10 @@
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#include <defs.h>
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#include <stub.c>
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#include "../bitbang/bitbang_functions.c"
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#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
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#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
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#define reg_oeb_userl (*(volatile uint32_t*)0x300FFFEC)
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#define reg_oeb_userh (*(volatile uint32_t*)0x300FFFE8)
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void main(){
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unsigned int i, j, k;
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reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
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@ -47,7 +50,10 @@ void main(){
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reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_PULLUP;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLUP;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_PULLUP;
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reg_mprj_userl = 0xFFFFFFFF;
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reg_mprj_userh = 0x3F;
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reg_oeb_userl = 0x0;
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reg_oeb_userh = 0x0;
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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@ -50,8 +50,6 @@ void main(){
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reg_mprj_io_1 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_io_0 = GPIO_MODE_USER_STD_INPUT_NOPULL;
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reg_mprj_userl = 0xFFFFFFFF;
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reg_mprj_userh = 0x3F;
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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@ -4,7 +4,8 @@
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// Debug reg DEBUG_ON
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#define reg_mprj_userl (*(volatile uint32_t*)0x300FFFF0)
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#define reg_mprj_userh (*(volatile uint32_t*)0x300FFFF4)
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#define reg_oeb_userl (*(volatile uint32_t*)0x300FFFEC)
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#define reg_oeb_userh (*(volatile uint32_t*)0x300FFFE8)
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void main(){
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unsigned int i, j, k;
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reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
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@ -53,7 +54,8 @@ void main(){
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reg_mprj_xfer = 1;
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while (reg_mprj_xfer == 1);
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reg_oeb_userl = 0x0;
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reg_oeb_userh = 0x0;
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reg_debug_1 = 0xAA; // finish configuration
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reg_mprj_userl = 0x0;
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reg_mprj_userh = 0x0;
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@ -354,3 +354,113 @@ async def gpio_all_i_pd_user(dut):
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if gpio[i] != "0":
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cocotb.log.error(f"[TEST] gpio[{i}] is having wrong value {gpio[i]} instead of 0 while configured as input pulldown and all released")
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await ClockCycles(caravelEnv.clk,1000)
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@cocotb.test()
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@repot_test
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async def gpio_all_bidir_user(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=290455)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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uut = dut.uut
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await wait_reg1(cpu,caravelEnv,0x1A)
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cocotb.log.info("[TEST] finish configuring ")
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i= 0x20
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for j in range(5):
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await wait_reg2(cpu,caravelEnv,37-j)
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
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if caravelEnv.monitor_gpio((37,0)).integer != i << 32:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,0))} instead of {bin(i << 32)}')
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await wait_reg2(cpu,caravelEnv,0)
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if caravelEnv.monitor_gpio((37,0)).integer != 0:
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cocotb.log.error(f'[TEST] Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x20
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i= 0x80000000
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for j in range(32):
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await wait_reg2(cpu,caravelEnv,32-j)
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cocotb.log.info(f'[Test] gpio out = {caravelEnv.monitor_gpio((37,0))} j = {j}')
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if caravelEnv.monitor_gpio((37,32)).integer != 0x3f:
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cocotb.log.error(f'[TEST] Wrong gpio high bits output {caravelEnv.monitor_gpio((37,32))} instead of {bin(0x3f)} ')
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if caravelEnv.monitor_gpio((31,0)).integer != i :
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cocotb.log.error(f'[TEST] Wrong gpio low bits output {caravelEnv.monitor_gpio((31,0))} instead of {bin(i)}')
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await wait_reg2(cpu,caravelEnv,0)
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if caravelEnv.monitor_gpio((37,0)).integer != 0:
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cocotb.log.error(f'Wrong gpio output {caravelEnv.monitor_gpio((37,0))} instead of {bin(0x00000)}')
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i = i >> 1
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i |= 0x80000000
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caravelEnv.release_gpio((37,0))
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await ClockCycles(caravelEnv.clk, 10)
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caravelEnv.drive_gpio_in((31,0),0)
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await ClockCycles(caravelEnv.clk, 10)
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await wait_reg1(cpu,caravelEnv,0xAA)
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cocotb.log.info(f"[TEST] configuration finished")
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data_in = 0xFFFFFFFF
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
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caravelEnv.drive_gpio_in((31,0),data_in)
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await wait_reg1(cpu,caravelEnv,0xBB)
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if cpu.read_debug_reg2() == data_in:
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
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else:
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cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
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data_in = 0xAAAAAAAA
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
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caravelEnv.drive_gpio_in((31,0),data_in)
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await wait_reg1(cpu,caravelEnv,0xCC)
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if cpu.read_debug_reg2() == data_in:
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
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else:
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cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
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data_in = 0x55555555
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
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caravelEnv.drive_gpio_in((31,0),data_in)
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await wait_reg1(cpu,caravelEnv,0xDD)
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if cpu.read_debug_reg2() == data_in:
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
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else:
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cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
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data_in = 0x0
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[31:0]")
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caravelEnv.drive_gpio_in((31,0),data_in)
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await wait_reg1(cpu,caravelEnv,0xD1)
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if cpu.read_debug_reg2() == data_in:
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[31:0]")
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else:
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cocotb.log.error(f"[TEST] Error: reg_mprj_datal has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
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data_in = 0x3F
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
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caravelEnv.drive_gpio_in((37,32),data_in)
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await wait_reg1(cpu,caravelEnv,0xD2)
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if cpu.read_debug_reg2() == data_in:
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
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else:
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cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
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data_in = 0x0
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
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caravelEnv.drive_gpio_in((37,32),data_in)
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await wait_reg1(cpu,caravelEnv,0xD3)
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if cpu.read_debug_reg2() == data_in:
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
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else:
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cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
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data_in = 0x15
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
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caravelEnv.drive_gpio_in((37,32),data_in)
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await wait_reg1(cpu,caravelEnv,0xD4)
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if cpu.read_debug_reg2() == data_in:
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cocotb.log.info(f"[TEST] data {hex(data_in)} sent successfully through gpio[37:32]")
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else:
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cocotb.log.error(f"[TEST] Error: reg_mprj_datah has recieved wrong data {cpu.read_debug_reg2()} instead of {data_in}")
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data_in = 0x2A
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cocotb.log.info(f"[TEST] drive {hex(data_in)} to gpio[37:32]")
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caravelEnv.drive_gpio_in((37,32),data_in)
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await wait_reg1(cpu,caravelEnv,0XD5)
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await wait_reg2(cpu,caravelEnv,0XFF)
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cocotb.log.info(f"[TEST] finish")
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await ClockCycles(caravelEnv.clk, 10)
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@ -91,7 +91,7 @@ class RunTest:
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macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
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if self.test_name == "la":
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macros = f'{macros} +define+LA_TESTING'
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if self.test_name in ["gpio_all_o_user","gpio_all_i_user","gpio_all_i_pu_user","gpio_all_i_pd_user"]:
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if self.test_name in ["gpio_all_o_user","gpio_all_i_user","gpio_all_i_pu_user","gpio_all_i_pd_user","gpio_all_bidir_user"]:
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macros = f'{macros} +define+GPIO_TESTING'
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# shutil.copyfile(f'{self.test_full_dir}/{self.test_name}.hex',f'{self.sim_path}/{self.test_name}.hex')
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# if os.path.exists(f'{self.test_full_dir}/test_data'):
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@ -45,26 +45,40 @@ module user_project_gpio_example (
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);
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reg [31:0] io_l;
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reg [5:0] io_h;
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reg [31:0] oeb_l;
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reg [5:0] oeb_h;
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always @(posedge wb_clk_i or posedge wb_rst_i) begin
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||||
if (wb_rst_i) begin
|
||||
io_l <=0;
|
||||
io_h <=0;
|
||||
oeb_l <=0;
|
||||
oeb_h <=0;
|
||||
wbs_dat_o <=0;
|
||||
wbs_ack_o <=0;
|
||||
end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0))begin // write
|
||||
|
||||
end else if (wbs_cyc_i && wbs_stb_i && wbs_we_i && !wbs_ack_o && (wbs_adr_i[31:0]==32'h300FFFF4||wbs_adr_i[31:0]==32'h300FFFF0||wbs_adr_i[31:0]==32'h300FFFEC||wbs_adr_i[31:0]==32'h300FFFE8))begin // write
|
||||
// write to io_l
|
||||
io_l[7:0] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[0])? wbs_dat_i[7:0] :io_l[7:0];
|
||||
io_l[15:8] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[1])? wbs_dat_i[15:8] :io_l[15:8];
|
||||
io_l[23:16] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[2])? wbs_dat_i[23:16] :io_l[23:16];
|
||||
io_l[31:24] <= ((wbs_adr_i[3:0]==4'h0) && wbs_sel_i[3])? wbs_dat_i[31:24] :io_l[31:24];
|
||||
io_l[7:0] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[0])? wbs_dat_i[7:0] :io_l[7:0];
|
||||
io_l[15:8] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[1])? wbs_dat_i[15:8] :io_l[15:8];
|
||||
io_l[23:16] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[2])? wbs_dat_i[23:16] :io_l[23:16];
|
||||
io_l[31:24] <= ((wbs_adr_i[31:0]==32'h300FFFF0) && wbs_sel_i[3])? wbs_dat_i[31:24] :io_l[31:24];
|
||||
// io_h
|
||||
io_h[5:0] <= ((wbs_adr_i[3:0]==4'h4) && wbs_sel_i[0])? wbs_dat_i[5:0] :io_h[5:0];
|
||||
io_h[5:0] <= ((wbs_adr_i[31:0]==32'h300FFFF4) && wbs_sel_i[0])? wbs_dat_i[5:0] :io_h[5:0];
|
||||
// oeb_l
|
||||
oeb_l[7:0] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[0])? wbs_dat_i[7:0] :oeb_l[7:0];
|
||||
oeb_l[15:8] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[1])? wbs_dat_i[15:8] :oeb_l[15:8];
|
||||
oeb_l[23:16] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[2])? wbs_dat_i[23:16] :oeb_l[23:16];
|
||||
oeb_l[31:24] <= ((wbs_adr_i[31:0]==32'h300FFFEC) && wbs_sel_i[3])? wbs_dat_i[31:24] :oeb_l[31:24];
|
||||
// oeb_h
|
||||
oeb_h[7:0] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[0])? wbs_dat_i[7:0] :oeb_h[7:0];
|
||||
oeb_h[15:8] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[1])? wbs_dat_i[15:8] :oeb_h[15:8];
|
||||
oeb_h[23:16] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[2])? wbs_dat_i[23:16] :oeb_h[23:16];
|
||||
oeb_h[31:24] <= ((wbs_adr_i[31:0]==32'h300FFFE8) && wbs_sel_i[3])? wbs_dat_i[31:24] :oeb_h[31:24];
|
||||
|
||||
wbs_ack_o <= 1;
|
||||
end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[3:0]==4'h4||wbs_adr_i[3:0]==4'h0)) begin // read
|
||||
wbs_dat_o <= (wbs_adr_i[3:0]==4'h0)? io_in[31:0] : io_in[`MPRJ_IO_PADS-1:32];
|
||||
end else if (wbs_cyc_i && wbs_stb_i && !wbs_we_i && !wbs_ack_o && (wbs_adr_i[31:0]==32'h300FFFF4||wbs_adr_i[31:0]==32'h300FFFF0||wbs_adr_i[31:0]==32'h300FFFEC||wbs_adr_i[31:0]==32'h300FFFE8)) begin // read
|
||||
wbs_dat_o <= (wbs_adr_i[31:0]==32'h300FFFF0)? io_in[31:0] :(wbs_adr_i[31:0]==32'h300FFFF4)? io_in[`MPRJ_IO_PADS-1:32] : (wbs_adr_i[31:0]==32'h300FFFEC) ? io_oeb[31:0]: io_oeb[37:32];
|
||||
wbs_ack_o <= 1;
|
||||
end else begin
|
||||
wbs_ack_o <= 0;
|
||||
|
|
@ -73,7 +87,7 @@ module user_project_gpio_example (
|
|||
end
|
||||
|
||||
assign io_out = {io_h,io_l};
|
||||
assign io_oeb = 38'h0;
|
||||
assign io_oeb = {oeb_h,oeb_l};
|
||||
|
||||
endmodule
|
||||
|
||||
|
|
|
|||
|
|
@ -108,42 +108,42 @@ wire [31:0] wbs_dat_o_gpio;
|
|||
wire [31:0] wbs_dat_o_debug;
|
||||
|
||||
// reserve the last 2 regs for debugging registers
|
||||
`ifndef GPIO_TESTING
|
||||
// `ifndef GPIO_TESTING
|
||||
assign wbs_cyc_i_user = (wbs_adr_i[31:3] != 29'h601FFFF) ? wbs_cyc_i : 0;
|
||||
assign wbs_cyc_i_debug = (wbs_adr_i[31:3] == 29'h601FFFF) ? wbs_cyc_i : 0;
|
||||
`endif
|
||||
// `endif
|
||||
|
||||
|
||||
`ifndef GPIO_TESTING
|
||||
assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_debug;
|
||||
// `ifndef GPIO_TESTING
|
||||
assign wbs_ack_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_ack_o_debug : wbs_ack_o_user;
|
||||
assign wbs_dat_o = (wbs_adr_i[31:3] == 28'h601FFFF) ? wbs_dat_o_debug : wbs_dat_o_user;
|
||||
`endif
|
||||
// `endif
|
||||
|
||||
|
||||
// reserve the last 4 regs for debugging registers in case of user gpio testing
|
||||
`ifdef GPIO_TESTING
|
||||
assign wbs_cyc_i_user = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0;
|
||||
assign wbs_cyc_i_debug = (wbs_adr_i[31:4] == 28'h300FFFF) ? wbs_cyc_i : 0;
|
||||
`endif
|
||||
// // reserve the last 4 regs for debugging registers in case of user gpio testing
|
||||
// `ifdef GPIO_TESTING
|
||||
// assign wbs_cyc_i_user = (wbs_adr_i[31:4] != 28'h300FFFF) ? wbs_cyc_i : 0;
|
||||
// assign wbs_cyc_i_debug = (wbs_adr_i[31:4] == 28'h300FFFF) ? wbs_cyc_i : 0;
|
||||
// `endif
|
||||
|
||||
`ifdef GPIO_TESTING
|
||||
assign wbs_ack_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_ack_o_debug : wbs_ack_o_gpio : wbs_ack_o_debug;
|
||||
assign wbs_dat_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_dat_o_debug : wbs_dat_o_gpio : wbs_dat_o_user;
|
||||
`endif
|
||||
// `ifdef GPIO_TESTING
|
||||
// assign wbs_ack_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_ack_o_debug : wbs_ack_o_gpio : wbs_ack_o_debug;
|
||||
// assign wbs_dat_o = (wbs_adr_i[31:4] == 28'h300FFFF) ? (wbs_adr_i[3:0]>=4'h8) ? wbs_dat_o_debug : wbs_dat_o_gpio : wbs_dat_o_user;
|
||||
// `endif
|
||||
|
||||
|
||||
`ifdef GPIO_TESTING
|
||||
user_project_gpio_example gpio_testing(
|
||||
.wb_clk_i(wb_clk_i),
|
||||
.wb_rst_i(wb_rst_i),
|
||||
.wbs_cyc_i(wbs_cyc_i_debug),
|
||||
.wbs_cyc_i(wbs_cyc_i_user),
|
||||
.wbs_stb_i(wbs_stb_i),
|
||||
.wbs_we_i(wbs_we_i),
|
||||
.wbs_sel_i(wbs_sel_i),
|
||||
.wbs_adr_i(wbs_adr_i),
|
||||
.wbs_dat_i(wbs_dat_i),
|
||||
.wbs_ack_o(wbs_ack_o_gpio),
|
||||
.wbs_dat_o(wbs_dat_o_gpio),
|
||||
.wbs_ack_o(wbs_ack_o_user),
|
||||
.wbs_dat_o(wbs_dat_o_user),
|
||||
.io_in(io_in),
|
||||
.io_out(io_out),
|
||||
.io_oeb(io_oeb));
|
||||
|
|
|
|||
Loading…
Reference in New Issue