Commit Graph

521 Commits

Author SHA1 Message Date
marwaneltoukhy 1236f44456 updated physical verification reports 2023-04-26 17:33:44 +02:00
mo-hosni 907937b20f reharden `caravel_core` using the updated `gpio_defaults_block` 2023-04-20 23:17:38 -07:00
mo-hosni 2b8e7b7e2e reharden `caravel_core` to have `user_id_programming` as a macro 2023-04-20 07:26:58 -07:00
mo-hosni 94a68ad071 update the physical views for `caravel_core` as the previous ones had issues in integration 2023-04-11 07:43:05 -07:00
mo-hosni bd20921b90 reharden `caravel_core` using a newer OpenLane version 2023-04-10 07:14:59 -07:00
mo-hosni 4398773262 reharden `housekeeping` using a newer OpenLane version 2023-04-10 07:13:48 -07:00
mo-hosni 58bc32467d reharden `caravel_core` to fix 1 hold violation at the fast nominal corner. 2023-03-27 04:44:22 -07:00
mo-hosni 05795a470f reharden `caravel_core` 2023-03-26 02:56:12 -07:00
mo-hosni f233f2f708 reharden housekeeping to fix setup violations at the ss-max corner on top-level. 2023-03-13 02:53:49 -07:00
mo-hosni 360b7d4cf2 Reharden `caravel_core`. 2023-03-06 01:24:00 -08:00
mo-hosni bf18ce8985 remove old gate-level netlists. 2023-03-05 01:04:37 -08:00
mo-hosni 3ccbad56dd reharden `caravel_core`. 2023-03-05 00:59:13 -08:00
mo-hosni 725698014a reharden caravel_core after fixing an issue in the RTL of RAM256. 2023-02-28 05:51:06 -08:00
mo-hosni 7fdcd0d930 add missing GLs. 2023-02-27 11:44:04 -08:00
mo-hosni 7c6e956221 reharden caravel using the modified chip_io. 2023-02-27 11:19:33 -08:00
mo-hosni 25e96c9d62 reharden caravel. 2023-02-27 10:39:51 -08:00
mo-hosni 9be48c6a7b implementation of caravel_core. 2023-02-27 10:38:06 -08:00
mo-hosni e560b56db5 reharden spare_logic_block. 2023-02-27 10:37:00 -08:00
mo-hosni 3f29ea49e7 harden mprj_io_buffer. 2023-02-27 10:33:48 -08:00
mo-hosni 5f8e954d95 reharden gpio_logic_high. 2023-02-27 10:29:46 -08:00
mo-hosni 86612d1f08 reharden caravel_clocking. 2023-02-27 10:26:19 -08:00
mo-hosni 7067304fd9 Added manual_power_connections. 2023-02-27 08:15:35 -08:00
mo-hosni 0952575c9d Add empty_macro which acts as a placement obstruction. 2023-02-27 08:14:55 -08:00
mo-hosni 8d6cfe6e2b reharden gpio_defaults_block. Changed the power stripes to be on Metal3. 2023-02-27 07:34:33 -08:00
mo-hosni 50a762407b re-implementation of housekeeping. Fixed maximum transition and antenna violations. 2023-02-27 07:30:03 -08:00
Passant b463e533ec update caravel rtl/hierarchy:
+ add `mprj_io_buffer` module that is used to guide the router and buffer signals going to the IOs far from the housekeeping
+ add `caravel_core` rtl that includes all the macros of caravel
~ restructure caravel to `caravel_core` and `chip_io` that includes the padframe
~ update `caravel_clocking` rtl to include `porb` input reset signal from power-on-reset
~ update `gpio_control_block` rtl to buffer `serial_clock` and `serial_load` siganls
2023-02-26 13:43:37 +02:00
Jeff DiCorpo bde8c9ef5e
Merge pull request #391 from efabless/fix_housekeeping_serial_fsm
Update serial configuration fsm to reset the transfer bit
2023-01-05 22:19:18 -08:00
Anton Blanchard 25e5e27f9d Fix issues with port definitions
Caravel fails to build with recent Icarus Verilog versions because some of
the port definitions are not valid.
2023-01-05 20:53:17 +11:00
M0stafaRady c23af382ae Update serial configuration fsm to reset the transfer bit 2022-11-20 04:27:40 -08:00
Tim Edwards d1f47cc451 Fixes the user defines configuration values for pullup and pulldown
modes to match the correct ones that are in defs.h in the management
SoC LiteX repository.  See caravel issue #380.
2022-11-16 09:36:01 -05:00
Jeff DiCorpo 748fbed12e
Merge pull request #377 from d-m-bailey/gpio_doc_fix
fixed documentation for gpio's used in caravan
2022-11-15 12:26:11 -08:00
D. Mitch Bailey 2c099c099e fixed documentation for gpio's used in caravan 2022-11-11 08:22:20 -08:00
Kareem Farid 44ffff2811 bugfix: remove extra comma after the last port in the decaps declaration 2022-11-07 13:00:00 +02:00
Kareem Farid d14035d8a2 gpio_signal_buffering rtl decaps
+ add sky130_ef_sc_hd__decap_12 decaps in the rtl of gpio_signal_buffering
+ add sky130_ef_sc_hd__decap_12 stub file for openlane; there is no
yosys-parseable verilog model for sky130_ef_sc_hd__decap_12
~ change config of gpio_signal_buffering* to add sky130_ef_sc_hd__decap_12
~ regenerate the gl netlist based on the above changes
2022-11-01 19:16:53 +02:00
M0stafaRady 0da9e78e57 Update cocotb README file to include PDK export requirements 2022-10-30 01:47:46 -07:00
M0stafaRady 1e385b6e23 Merge branch 'main' into cocotb 2022-10-30 01:36:41 -07:00
marwaneltoukhy c824608e25 Merge branch 'main' into caravel_redesign-2 2022-10-28 13:33:35 -07:00
mo-hosni b5010be8a7 Update Openlane views 2022-10-27 09:53:45 -07:00
mo-hosni 2d61e593aa Decreased distances from pins to and gates in mgmt_protect 2022-10-27 08:20:57 -07:00
M0stafaRady 6f92625192 cocotb - update bitbang tests for caravan 2022-10-25 16:30:42 -07:00
M0stafaRady 4bd0f5bec1 Adding bitbang tests to caravan regression 2022-10-25 14:21:18 -07:00
M0stafaRady 693c9e5538 Merge branch 'caravan-signoff' into cocotb 2022-10-25 08:03:15 -07:00
M0stafaRady 745b3e3e2c cocotb - skip write and read from xfer
because the write reg is diffrent than the read one
2022-10-25 08:00:51 -07:00
M0stafaRady 83a2e0d6c2 cocotb - remove pll and clock_redirect tests from caravan regression
because gpio 15 and 16 are used as analog bins and tests used them for redirect
increase the timeout for mgmt_gpio_bidir test
2022-10-24 13:16:38 -07:00
Marwan Abbas 18d779f5cd removed caravel-eco.v gl netlist and added the eco for porb_h_in in caravel.v 2022-10-24 17:58:50 +02:00
M0stafaRady add686f220 cocotb add gl and sdf regression for caravan 2022-10-24 08:27:27 -07:00
M0stafaRady 655232b37d merge with main 2022-10-24 07:51:16 -07:00
M0stafaRady a507c7ddd3 cocotb - update verify_cocotb to run caravan with vcs 2022-10-24 07:46:33 -07:00
M0stafaRady 45978f5304 cocotb - Adding cpu_reset test 2022-10-24 06:39:34 -07:00
M0stafaRady 425b59249d cocotb - Fix timeout of all tests 2022-10-24 04:59:04 -07:00
M0stafaRady 0d30276afa cocotb - fix include of vcs rtl code to enable the coverage for RTL 2022-10-23 08:13:17 -07:00
M0stafaRady 523fa3a5bb
cooctb- update gpio tests for caravan (#341)
* update gpio tests for caravan

* cocotb - Add gpio caravan tests
2022-10-22 12:14:25 -07:00
R. Timothy Edwards 30d35947f1
Added decap cells to the gate-level verilog for the (#343)
gpio_signal_buffering_alt cell (caravan chip).  This was
previously done for gpio_signal_buffering (caravel chip) but
the same thing had not previously been done for caravan.
2022-10-22 12:12:06 -07:00
M0stafaRady 8051e22ad2 cocotb - Add gpio caravan tests 2022-10-22 11:09:23 -07:00
M0stafaRady 900e66a804 update gpio tests for caravan 2022-10-22 11:04:04 -07:00
marwaneltoukhy 66b7293817 signoff views for caravan 2022-10-22 07:01:29 -07:00
kareem 0be31a26c1 reharden: caravan
~ reimplement after rtl changes
2022-10-22 02:52:02 -07:00
R. Timothy Edwards d9260dc533
Fixes to caravan for LVS and ERC (#330)
* Corrected missing part of porb_h route in the caravan chip_io_alt
layout.  Correcting the indexing of the "mprj_io_one" connections
to "mgmt_io_oeb" on the left-hand side of caravan, as they were
connecting back to the right side and making a mess of wiring,
instead of being wired locally directly to the nearest I/O.

* Apply automatic changes to Manifest and README.rst

* Corrected the unconnected mgmt_io_in inputs to housekeeping on
the caravan chip (which correspond to the GPIOs that do not exist
in caravan) by connecting them to the "zero" outputs of the
closest GPIO control blocks.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-10-21 14:28:53 -07:00
Marwan Abbas 7db65f3e32
Added gl netlists for chip_io_alt and gpio_signal_buffering_alt (#327) 2022-10-21 12:06:20 -07:00
passant5 0c9e3a08fd
update caravel with tying `porb_h_in` with `por_l_in` (#326)
* update caravel with tying `porb_h_in` with `por_l_in` at the `mgmt_core_wrapper` in the top-level layout:
- `porb_h_in` shouldn't be left floating as it is an input to `clkbuf_16`

* add caravel-eco.gds (same as caravel.gds)
2022-10-21 11:52:00 -07:00
R. Timothy Edwards 5029d71df6
Syntax changes that are non-functional from a synthesis perspective. (#324)
* Syntax changes that are non-functional from a synthesis perspective.
There are a few errors that are caught by commercial tools and halt
synthesis, which are handled more gracefully by the open source
tool flow.  In housekeeping.v:  Some wires declared after they are
used.  In housekeeping_spi.v:  A non-blocking "=" assignment used
where a blocking "<-" assignment was intended.

* Apply automatic changes to Manifest and README.rst

Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
2022-10-21 10:10:20 -07:00
M0stafaRady 096f5035f5
cocotb - updates related to enable simulating caraval using iverilog (#320)
* cocotb - updates related to enable simulating caraval using iverilog

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
2022-10-21 07:43:34 -07:00
Jeff DiCorpo 4192c34f4b
Caravan redesign (#321)
* Fixed caravan top level power routing and updated views for mag, gds and lef

* caravan(rtl): updates

~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog

* Apply automatic changes to Manifest and README.rst

* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script

* reharden: caravan

+ add non functional blocks
+ add an initial iteration of caravan

* Apply automatic changes to Manifest and README.rst

* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"

This reverts commit 70628f748a.

* fixed caravan top level power routing

* reharden: caravan

based on new power routing
~ guard rtl chip_io power pins in the power macro guard

* Apply automatic changes to Manifest and README.rst

* fixed caravan top level power routing

* rehadren: caravan

+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues

* Apply automatic changes to Manifest and README.rst

* fix power connection in buffering block and regenerate gl

* Apply automatic changes to Manifest and README.rst

* updated views for caravan

* Added extract unique to lvs-gds-cell target. (#313)

* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.

* Apply automatic changes to Manifest and README.rst

* reharden: caravan

~ rtl updated

* fixed caravan mag top level

* updated views for caravan + signoff

* fixed top level cell name

* fix syntax error related to signal initialization place in caravan (#319)

* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit

* Apply automatic changes to Manifest and README.rst

Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>

* Apply automatic changes to Manifest and README.rst

Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
2022-10-21 07:37:41 -07:00
M0stafaRady 9844ba5f21 cocotb - update documentation 2022-10-20 07:56:19 -07:00
M0stafaRady af9110c6dd cocotb - update verify_cocotb.py script to fully support running with iverilog in RTL and GL mode 2022-10-20 06:28:07 -07:00
M0stafaRady 98d089ed08 Move decleration of some signal in caravel.v to fix error in iverilog 2022-10-20 06:26:55 -07:00
M0stafaRady 891afe841b Merge branch 'caravel_redesign' into cocotb 2022-10-20 01:35:16 -07:00
Marwan Abbas 71b1faabc5
Caravel final views (#310)
* added views for each step of generating final caravel.gds

* generated the right caravel and caravel-eco gds

* renamed caravel_signoff and removed caravel-non-eco

Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
2022-10-19 18:27:26 -07:00
M0stafaRady 23b2045abe
consider test debug be use only dff in linkerscript since test write to the dff2 ram and align the addresses generated (#308) 2022-10-19 12:29:24 -07:00
Marwan Abbas bbb6bf775c
Caravel redesign new top (#300)
* reharden: caravel

~ shift caravel_clocking due to change in size
~ change the pr boundary of caravel_power_routing mag file
~ regenarate lef of caravel_power_routing

* update pdn for `caravel_clocking` & `digital_pll`

* added script to update and generate the power routing views

* ~ run update_power_routing_views from the caravel root with prboundary

* fix output message

* added power routing lef, mag and gds

* fix update_power_routing_views saving wrong cell name

* reharden: caravel

~ incorperate pdn changes
~ re-extract spefs

* fix caravel_power_routing views

* fix abs path in maglef views

* fix abs path in mag views
add substcut layers in gpio_control_block and mgmt_protect

* generate a new chip_io gds

* regenerate gpio_control_block due to mag and gds not in sync

* reharden: caravel

~ change config to pass clean routing
~ use updated views of macros

* lvs clean views

* add caravel top-level generated sdf for all corners

* fix absolute path for mgmt_core_wrapper

Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: Bassant Hassan <bassant.hassan@efabless.com>
2022-10-18 17:24:07 -07:00
M0stafaRady 9d1e4b35d7
Merge pull request #298 from efabless/cocotb-dev
cocotb - update script to store git info in the run git_show.log
2022-10-19 00:45:09 +02:00
M0stafaRady 340f776e46 cocotb - update script to store git info in the run git_show.log 2022-10-18 12:27:42 -07:00
M0stafaRady d13743ae41 cocotb - Add spi_rd_wr_nbyte test 2022-10-18 11:43:40 -07:00
Marwan Abbas 4b9df5271b
Merge pull request #287 from efabless/cocotb-dev
cocotb - ziping passed waves instead of removing them and fix bug at debug test
2022-10-18 17:15:50 +02:00
Marwan Abbas 38902bde45
Merge pull request #292 from efabless/caravel-redesign-digital_pll-decaps
reharden: digital_pll
2022-10-18 16:35:49 +02:00
Marwan Abbas 4cbf8ca4f6
Merge pull request #291 from efabless/caravel-redesign-clocking-decaps
reharden: caravel_clocking
2022-10-18 16:35:26 +02:00
kareem 68063ddadc reharden: digital_pll
~ increase width for more spread decaps
+ add or cells to cell exclude
~ change placement density in accordance to area
~ change padding to allow for space for decaps
2022-10-18 07:07:32 -07:00
kareem fdeb6003f3 Merge branch 'caravel_redesign-digital_pll-no-or' into caravel_redesign 2022-10-18 06:31:00 -07:00
kareem 3bd586b50c reharden: caravel_clocking
~ increase height for more spread decap insertion
+ add or cells to cell exclude
~ adjust pdn to have an offset half to pitch
~ change placement density in accordance to area
~ change padding to allow for space for decap insertion
2022-10-18 06:18:30 -07:00
mo-hosni 1110ae2fe8 update housekeeping views and openlane configuration 2022-10-18 04:07:27 -07:00
M0stafaRady 2a05ee19ae cocotb - fix bug at debug test for gate level 2022-10-18 03:49:45 -07:00
M0stafaRady d444c279b0 Merge branch 'caravel_redesign' into cocotb-dev 2022-10-18 03:46:47 -07:00
M0stafaRady 37beb80c50 Merge branch 'cocotb-dev' into cocotb 2022-10-18 03:14:45 -07:00
M0stafaRady 13c2f299d0 cocotb - update script to keep the test log when test pass 2022-10-18 03:12:58 -07:00
M0stafaRady c7df730c0a cocotb - ziping passed waves instead of removing them 2022-10-18 02:56:31 -07:00
kareem 712b784e16 reharden!: digital_pll
~ disable or gate
+ add nosynth list file
2022-10-17 12:33:25 -07:00
Mohamed Shalan 3fbc52ecbf
Merge pull request #276 from efabless/caravel_redesign-digital_pll-fanout
reharden!: digital_pll
2022-10-17 20:50:01 +02:00
mo-hosni 2d147966b9 Update housekeeping views and openlane configuration 2022-10-17 11:37:24 -07:00
kareem e5d9788a43 reharden!: digital_pll
~ enable synth buffering to fix fanout
~ add *buf_1* to no synth list
~ add attribute (* keep *) to the oscillator as dont
touch for yosys

!need to verify that the oscillator remains untouched
2022-10-17 10:56:01 -07:00
Passant 9c3fea9a4d update caravel top-level rtl to not buffer `porb_h` through the `mgmt_core_wrapper` 2022-10-17 10:46:31 -07:00
M0stafaRady 0f174d897f
Merge pull request #269 from efabless/cocotb
cocotb - fix debug test
2022-10-17 18:01:24 +02:00
M0stafaRady cf1519b929 cocotb - add debug test to regression lists 2022-10-17 08:57:20 -07:00
M0stafaRady b5234b269f fix debug test 2022-10-17 08:29:39 -07:00
M0stafaRady 4bbf9938c9
Merge pull request #266 from efabless/cocotb-dev
Cocotb - add delay at the test mgmt_gpio_bidir test
2022-10-17 16:47:11 +02:00
M0stafaRady 55eaf936b0 Cocotb - add delay at the test mgmt_gpio_bidir test 2022-10-17 04:35:29 -07:00
kareem a8794dff4b reharden: caravel
~ reharden with updated pdn
~ add stubs for non functional blocks
2022-10-17 03:59:28 -07:00
M0stafaRady de11170ab2 fix syntax error at gl/gpio_signal_buffering.v 2022-10-17 00:55:12 -07:00
marwaneltoukhy 2d28c973ee added views for caravel with power routing 2022-10-16 19:08:56 -07:00
marwaneltoukhy 7ec1eeb010 Merge branch 'caravel_redesign' into caravel_redesign-top-level 2022-10-16 18:39:39 -07:00
Marwan Abbas 35ec52aa72
Merge pull request #260 from efabless/fix_top_buffers_again
More changes to the GPIO buffer cell
2022-10-17 03:35:25 +02:00