fix syntax error at gl/gpio_signal_buffering.v

2022-10-17 00:55:12 -07:00 · 2022-10-17 00:55:12 -07:00 · de11170ab2
parent a915840efe
commit de11170ab2
1 changed files with 1 additions and 1 deletions
--- a/verilog/gl/gpio_signal_buffering.v
+++ b/verilog/gl/gpio_signal_buffering.v
@ -1987,7 +1987,7 @@ module gpio_signal_buffering(vccd, vssd, mgmt_io_in_unbuf, mgmt_io_out_unbuf, mg
    .VGND(vssd),
    .VNB(vssd),
    .VPB(vccd),
-    .VPWR(vccd),
+    .VPWR(vccd)
  );

  /* End of hand-editing */