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Update serial configuration fsm to reset the transfer bit

This commit is contained in:
M0stafaRady 2022-11-20 04:27:40 -08:00
parent 10665aa1bf
commit c23af382ae
1 changed files with 9 additions and 0 deletions
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9
verilog/rtl/housekeeping.v
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@ -354,6 +354,7 @@ wire mgmt_gpio_out_9_prebuff, mgmt_gpio_out_14_prebuff, mgmt_gpio_out_15_prebuff
`define WBBD_SETUP3 4'h7 /* Apply address and data for byte 4 of 4 */
`define WBBD_RW3 4'h8 /* Latch data for byte 4 of 4 */
`define WBBD_DONE 4'h9 /* Send ACK back to wishbone */
`define WBBD_RESET 4'ha /* Clock once to reset the transfer bit */
assign sys_select = (wb_adr_i[31:8] == SYS_BASE_ADR[31:8]);
assign gpio_select = (wb_adr_i[31:8] == GPIO_BASE_ADR[31:8]);
@ -671,6 +672,7 @@ wire mgmt_gpio_out_9_prebuff, mgmt_gpio_out_14_prebuff, mgmt_gpio_out_15_prebuff
end else begin
case (wbbd_state)
`WBBD_IDLE: begin
wbbd_sck <= 1'b0;
wbbd_busy <= 1'b0;
if ((sys_select | gpio_select | spi_select) &&
wb_cyc_i && wb_stb_i) begin
@ -759,6 +761,13 @@ wire mgmt_gpio_out_9_prebuff, mgmt_gpio_out_14_prebuff, mgmt_gpio_out_15_prebuff
wbbd_sck <= 1'b0;
wb_ack_o <= 1'b0; // Reset for next access
wbbd_write <= 1'b0;
wbbd_state <= `WBBD_RESET;
end
`WBBD_RESET: begin
wbbd_busy <= 1'b1;
wbbd_sck <= 1'b1;
wb_ack_o <= 1'b0;
wbbd_write <= 1'b0;
wbbd_state <= `WBBD_IDLE;
end
endcase