mirror of https://github.com/efabless/caravel.git
cocotb - update verify_cocotb.py script to fully support running with iverilog in RTL and GL mode
This commit is contained in:
M0stafaRady
parent
98d089ed08
commit
af9110c6dd
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@ -1,79 +0,0 @@
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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#
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# SPDX-License-Identifier: Apache-2.0
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PWDD := $(shell pwd)
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BLOCKS := $(shell basename $(PWDD))
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# ---- Include Partitioned Makefiles ----
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CONFIG = caravel_user_project
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# TestName = temp_partial
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# export COCOTB_ANSI_OUTPUT=0 # disable color in termianl
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export GUI=1
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export COCOTB_REDUCED_LOG_FMT=1
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# Change this line if you want to use existing cocotb test modules:
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# export PYTHONPATH := $(DESIGNS)/verilog/rtl/<your design python tests>
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# export LIBPYTHON_LOC=$(cocotb-config --libpython)
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#export VERILOG_PATH = ../../../
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#export CARAVEL_PATH = ../../../../../caravel/verilog/
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# include $(MCW_ROOT)/verilog/dv/make/env.makefile
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# #export VERILOG_PATH = ../../../
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# include $(MCW_ROOT)/verilog/dv/make/var.makefile
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# include $(MCW_ROOT)/verilog/dv/make/cpu.makefile
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# include $(MCW_ROOT)/verilog/dv/make/sim.makefile
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TESTCASE=$(TestName)
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MODULE=caravel_tests
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$(info $$MODULE is [$(MODULE)])
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cocotb:
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rm -rf sim_build/
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mkdir sim_build/
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# change project_tb.v to match your testbench
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#RTL
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iverilog -Ttyp -DFUNCTIONAL -DSIM -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
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-DTESTNAME=\"$(TestName)\" -DTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
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-f$(VERILOG_PATH)/includes/includes.rtl.caravel \
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-o sim_build/sim.vvp $(CARAVEL_PATH)/rtl/__user_project_wrapper.v $(CARAVEL_PATH)/rtl/debug_regs.v caravel_top.sv
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#GL
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# iverilog -Ttyp -DFUNCTIONAL -DGL -DUSE_POWER_PINS -DUNIT_DELAY=#1 \
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# -DTESTNAME=\"$(TestName)\" -DRUNTAG=\"$(RUNTAG)\" -DSIM=\"$(SIM)\" \
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# -f$(VERILOG_PATH)/includes/includes.gl.caravel \
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# -f$(USER_PROJECT_VERILOG)/includes/includes.gl.$(CONFIG) -o sim_build/sim.vvp caravel_top.sv
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#CVC
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# TESTCASE=$(TestName) MODULE=caravel_tests cvc64 +interp +acc+2 \
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# +loadvpi=$(shell cocotb-config --lib-name-path vpi cvc):vlog_startup_routines_bootstrap\
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# +change_port_type +maxerrors 1\
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# +define+SIM +define+FUNCTIONAL +define+GL +define+USE_POWER_PINS +define+UNIT_DELAY=#0 \
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# +define+TESTNAME=\"$(TestName)\" +define+RUNTAG=\"$(RUNTAG)\" +define+COCOTB_SIM=1\
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# -f $(VERILOG_PATH)/includes/includes.gl+sdf.caravel \
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# -f $(USER_PROJECT_VERILOG)/includes/includes.gl+sdf.$(CONFIG) -o sim_build/sim.vvp
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# verilator --vpi --public-flat-rw --prefix Vtop \
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# -LDFLAGS "-Wl,-rpath,$(cocotb-config --prefix)/cocotb/libs \
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# -L$(cocotb-config --prefix)/cocotb/libs \
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# -lcocotbvpi_verilator -lgpi -lcocotb -lgpilog -lcocotbutils" \
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# $(cocotb-config --share)/lib/verilator/verilator.cpp\
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# -y $(VERILOG_PATH)/includes/includes.rtl.caravel \
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# -y $(USER_PROJECT_VERILOG)/includes/includes.rtl.$(CONFIG) --cc -o sim_build/sim.vvp caravel_top.sv
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# change this line to choose the comma separated test cases and the name of your python test module
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TESTCASE=$(TestName) MODULE=caravel_tests vvp -M $$(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus sim_build/sim.vvp
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! grep failure results.xml
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@ -12,7 +12,8 @@ import random
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from pathlib import Path
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import shutil
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from subprocess import PIPE, run
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import threading
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import time
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iverilog = True
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vcs = False
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@ -67,14 +68,21 @@ class RunTest:
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self.sim_path = f"sim/{os.getenv('RUNTAG')}/{test_dir}/"
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terminal_log=f"{self.sim_path}/fullTerminal.log"
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test_log=f"{self.sim_path}/{self.test_name}.log"
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self.full_terminal = open(test_log, "w")
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self.test_log=open(test_log, "w")
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self.full_file=f"{self.sim_path}/full.log"
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self.full_terminal = open(self.full_file, "w")
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def runTest(self):
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self.full_test_name = f"{self.sim_type}-{self.test_name}"
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if (self.sim_type=="GL_SDF"):
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self.full_test_name = f"{self.sim_type}-{self.test_name}-{self.corner}"
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os.environ["TESTFULLNAME"] = f"{self.full_test_name}"
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if (iverilog):return self.runTest_iverilog()
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elif(vcs): return self.runTest_vcs()
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# iverilog function
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def runTest_iverilog(self):
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print(f"Start running test: {self.sim_type}-{self.test_name}")
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CARAVEL_ROOT = os.getenv('CARAVEL_ROOT')
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CARAVEL_VERILOG_PATH = os.getenv('CARAVEL_VERILOG_PATH')
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MCW_ROOT = os.getenv('MCW_ROOT')
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@ -86,12 +94,39 @@ class RunTest:
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ERRORMAX = os.getenv('ERRORMAX')
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PDK_ROOT = os.getenv('PDK_ROOT')
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PDK = os.getenv('PDK')
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env_vars = f"-e {CARAVEL_ROOT} -e CARAVEL_VERILOG_PATH={CARAVEL_VERILOG_PATH} -e MCW_ROOT={MCW_ROOT} -e VERILOG_PATH={VERILOG_PATH} -e CARAVEL_PATH={CARAVEL_PATH} -e USER_PROJECT_VERILOG={USER_PROJECT_VERILOG} -e FIRMWARE_PATH={FIRMWARE_PATH} -e RUNTAG={RUNTAG} -e ERRORMAX={ERRORMAX} -e PDK_ROOT={PDK_ROOT} -e PDK={PDK}"
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print(f"Start running test: {self.sim_type}-{self.test_name}")
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command = f"TestName={self.test_name} SIM={self.sim_type} make cocotb >> {self.full_terminal.name} "
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os.system(f"docker run -it {env_vars} -v {os.getenv('CARAVEL_ROOT')}:{os.getenv('CARAVEL_ROOT')} -v {os.getenv('MCW_ROOT')}:{os.getenv('MCW_ROOT')} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {command}'")
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self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
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TESTFULLNAME = os.getenv('TESTFULLNAME')
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env_vars = f"-e {CARAVEL_ROOT} -e CARAVEL_VERILOG_PATH={CARAVEL_VERILOG_PATH} -e MCW_ROOT={MCW_ROOT} -e VERILOG_PATH={VERILOG_PATH} -e CARAVEL_PATH={CARAVEL_PATH} -e USER_PROJECT_VERILOG={USER_PROJECT_VERILOG} -e FIRMWARE_PATH={FIRMWARE_PATH} -e RUNTAG={RUNTAG} -e ERRORMAX={ERRORMAX} -e PDK_ROOT={PDK_ROOT} -e PDK={PDK} -e TESTFULLNAME={TESTFULLNAME}"
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macros = f'-DFUNCTIONAL -DSIM=\\\"{self.sim_type}\\\" -DUSE_POWER_PINS -DUNIT_DELAY=#1 -DMAIN_PATH=\\\"{self.cocotb_path}\\\" -DIVERILOG -DTESTNAME=\\\"{self.test_name}\\\" -DTAG=\\\"{RUNTAG}\\\" '
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if self.test_name == "la":
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macros = f'{macros} -DLA_TESTING'
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if self.test_name in ["gpio_all_o_user","gpio_all_i_user","gpio_all_i_pu_user","gpio_all_i_pd_user","gpio_all_bidir_user"]:
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macros = f'{macros} -DGPIO_TESTING'
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if(self.sim_type=="RTL"):
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includes = f"-f {VERILOG_PATH}/includes/includes.rtl.caravel"
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elif(self.sim_type=="GL"):
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macros = f'{macros} -DGL'
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includes = f"-f {VERILOG_PATH}/includes/includes.gl.caravel"
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elif(self.sim_type=="GLSDF"):
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print(f"iverilog can't run SDF for test {self.test_name} Please use anothor simulator like cvc" )
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return
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iverilog_command = (f"iverilog -Ttyp {macros} {includes} -o {self.sim_path}/sim.vvp"
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f" {CARAVEL_PATH}/rtl/__user_project_wrapper.v {CARAVEL_PATH}/rtl/__user_project_gpio_example.v {CARAVEL_PATH}/rtl/__user_project_la_example.v caravel_top.sv"
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f" && TESTCASE={self.test_name} MODULE=caravel_tests vvp -M $(cocotb-config --prefix)/cocotb/libs -m libcocotbvpi_icarus {self.sim_path}/sim.vvp")
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docker_command = f"docker run -it {env_vars} -v {os.getenv('CARAVEL_ROOT')}:{os.getenv('CARAVEL_ROOT')} -v {os.getenv('MCW_ROOT')}:{os.getenv('MCW_ROOT')} -v {os.getenv('PDK_ROOT')}:{os.getenv('PDK_ROOT')} efabless/dv:cocotb sh -c 'cd {self.cocotb_path} && {iverilog_command}' >> {self.full_file}"
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self.full_terminal = open(self.full_file, "a")
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self.full_terminal.write(f"docker command for running iverilog and cocotb:\n% ")
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self.full_terminal.write(os.path.expandvars(docker_command)+"\n")
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self.full_terminal.close()
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os.system(docker_command)
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self.passed = search_str(self.test_log.name,"Test passed with (0)criticals (0)errors")
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Path(f'{self.sim_path}/{self.passed}').touch()
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if self.passed == "passed":
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print(f"Test: {self.sim_type}-{self.test_name} passed")
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else :
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print(f"Test: {self.sim_type}-{self.test_name} Failed please check logs under {self.sim_path}")
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# vcs function
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def runTest_vcs(self):
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@ -104,7 +139,6 @@ class RunTest:
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dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/rtl_caravel_vcs.list\\\" '
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else:
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dirs = f' {dirs} -f \\\"{VERILOG_PATH}/includes/gl_caravel_vcs.list\\\" '
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full_test_name = f"{self.sim_type}-{self.test_name}"
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macros = f'+define+FUNCTIONAL +define+USE_POWER_PINS +define+UNIT_DELAY=#1 +define+MAIN_PATH=\\\"{self.cocotb_path}\\\" +define+VCS '
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if self.test_name == "la":
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macros = f'{macros} +define+LA_TESTING'
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@ -119,7 +153,6 @@ class RunTest:
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# os.makedirs(f"annotation_logs",exist_ok=True)
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dirs = f"{dirs} +incdir+\\\"{os.getenv('MCW_ROOT')}/verilog/\\\" "
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# +incdir+\\\"{os.getenv('CARAVEL_ROOT')}/signoff/caravel/primetime-signoff/\\\"
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full_test_name = f"{self.sim_type}-{self.test_name}-{self.corner}"
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elif(self.sim_type=="GL"):
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macros = f'{macros} +define+GL +define+SIM=GL'
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elif (self.sim_type=="RTL"):
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@ -132,11 +165,10 @@ class RunTest:
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os.environ["TESTCASE"] = f"{self.test_name}"
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os.environ["MODULE"] = f"caravel_tests"
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os.environ["SIM"] = self.sim_type
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os.environ["TESTFULLNAME"] = f"{full_test_name}"
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os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{full_test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
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os.system(f"vlogan -full64 -sverilog +error+30 caravel_top.sv {dirs} {macros} +define+TESTNAME=\\\"{self.test_name}\\\" +define+FTESTNAME=\\\"{self.full_test_name}\\\" +define+TAG=\\\"{os.getenv('RUNTAG')}\\\" -l {self.sim_path}/analysis.log -o {self.sim_path} ")
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os.system(f"vcs +lint=TFIPC-L {coverage_command} +error+30 -R -diag=sdf:verbose +sdfverbose +neg_tchk -debug_access -full64 -l {self.sim_path}/test.log caravel_top -Mdir={self.sim_path}/csrc -o {self.sim_path}/simv +vpi -P pli.tab -load $(cocotb-config --lib-name-path vpi vcs)")
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self.passed = search_str(self.full_terminal.name,"Test passed with (0)criticals (0)errors")
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self.passed = search_str(self.test_log.name,"Test passed with (0)criticals (0)errors")
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Path(f'{self.sim_path}/{self.passed}').touch()
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#delete wave when passed
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if self.passed == "passed" and zip_waves:
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@ -192,9 +224,11 @@ class RunTest:
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sed_command = f"sed -ie 's/@10/@00/g' {hex_file}"
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hex_gen_state = os.system(f"docker run -it -v {go_up(self.cocotb_path,4)}:{go_up(self.cocotb_path,4)} efabless/dv:latest sh -c 'cd {test_dir} && {elf_command} && {hex_command} && {sed_command} '")
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self.full_terminal.write(os.path.expandvars(elf_command)+"\n"+"\n")
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self.full_terminal.write(os.path.expandvars(hex_command)+"\n"+"\n")
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self.full_terminal.write(os.path.expandvars(sed_command)+"\n"+"\n")
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self.full_terminal.write("elf file generation command:\n% ")
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self.full_terminal.write(os.path.expandvars(elf_command)+"\n")
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self.full_terminal.write("hex file generation command:\n% ")
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self.full_terminal.write(os.path.expandvars(hex_command)+"\n% ")
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self.full_terminal.write(os.path.expandvars(sed_command)+"\n")
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self.cd_cocotb()
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self.full_terminal.close()
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if hex_gen_state != 0 :
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@ -307,30 +341,44 @@ class RunRegression:
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self.unknown_tests +=1
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def run_regression(self):
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threads = list()
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for test,sim_types in self.tests.items():
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for sim_type,corners in sim_types.items(): # TODO: add multithreading or multiprocessing here
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for corner,status in corners.items(): # TODO: add multithreading or multiprocessing here
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start_time = datetime.now()
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self.tests[test][sim_type][corner]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)")
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self.tests[test][sim_type][corner]["duration"] = "-"
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self.tests[test][sim_type][corner]["status"] = "running"
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self.update_reg_log()
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test_run = RunTest(test,sim_type,corner)
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self.tests[test][sim_type][corner]["status"] = "done"
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self.tests[test][sim_type][corner]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)")
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self.tests[test][sim_type][corner]["duration"] = ("%.10s" % (datetime.now() - start_time))
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self.tests[test][sim_type][corner]["pass"]= test_run.passed
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if test_run.passed == "passed":
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self.passed_tests +=1
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elif test_run.passed == "failed":
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self.failed_tests +=1
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self.unknown_tests -=1
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self.update_reg_log()
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for corner,status in corners.items():
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if iverilog: #threading
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# x = threading.Thread(target=self.test_run_function,args=(test,sim_type,corner))
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# threads.append(x)
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# x.start()
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# time.sleep(10)
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self.test_run_function(test,sim_type,corner)
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else:
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self.test_run_function(test,sim_type,corner)
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for index, thread in enumerate(threads):
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thread.join()
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if coverage:
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self.generate_cov()
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#TODO: add send mail here
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def test_run_function(self,test,sim_type,corner):
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start_time = datetime.now()
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self.tests[test][sim_type][corner]["starttime"] = datetime.now().strftime("%H:%M:%S(%a)")
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self.tests[test][sim_type][corner]["duration"] = "-"
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self.tests[test][sim_type][corner]["status"] = "running"
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self.update_reg_log()
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test_run = RunTest(test,sim_type,corner,)
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self.tests[test][sim_type][corner]["status"] = "done"
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self.tests[test][sim_type][corner]["endtime"] = datetime.now().strftime("%H:%M:%S(%a)")
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self.tests[test][sim_type][corner]["duration"] = ("%.10s" % (datetime.now() - start_time))
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self.tests[test][sim_type][corner]["pass"]= test_run.passed
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if test_run.passed == "passed":
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self.passed_tests +=1
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elif test_run.passed == "failed":
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self.failed_tests +=1
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self.unknown_tests -=1
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self.update_reg_log()
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def generate_cov(self):
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os.chdir(f"{self.cocotb_path}/sim/{os.getenv('RUNTAG')}")
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os.system(f"urg -dir RTL*/*.vdb -format both -show tests -report coverageRTL/")
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