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caravel
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update caravel top-level rtl to not buffer `porb_h` through the `mgmt_core_wrapper`

This commit is contained in:
Passant 2022-10-17 10:46:31 -07:00
parent 3311103692
commit 9c3fea9a4d
2 changed files with 50 additions and 5 deletions
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41
scripts/logs/rtl_caravel.log Normal file
View File

@ -0,0 +1,41 @@
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
sh: vlogan: command not found
sh: cocotb-config: command not found
sh: vcs: command not found
docker: Error response from daemon: OCI runtime start failed: container process is already dead: unknown.
time="2022-10-15T09:48:16-07:00" level=error msg="error waiting for container: context canceled"
^Cregression:r_rtl, test:None, testlist:None sim: ['RTL']
Run tag: CI_rtl
Start running test: RTL-bitbang_no_cpu_all_o
Start running test: RTL-bitbang_cpu_all_o
Start running test: RTL-gpio_all_o
Start running test: RTL-gpio_all_o_user
Start running test: RTL-gpio_all_i
Start running test: RTL-gpio_all_i_user
Start running test: RTL-gpio_all_i_pu
Start running test: RTL-gpio_all_i_pu_user
Start running test: RTL-gpio_all_i_pd
fatal: Error when generating hex

14
verilog/rtl/caravel.v
View File

@ -303,8 +303,8 @@ module caravel (
gpio_signal_buffering sigbuf (
`ifdef USE_POWER_PINS
.vccd(vccd),
.vssd(vssd),
.vccd(vccd_core),
.vssd(vssd_core),
`endif
.mgmt_io_in_unbuf(mgmt_io_in[37:7]),
.mgmt_io_out_unbuf(mgmt_io_out_hk[37:7]),
@ -361,7 +361,7 @@ module caravel (
.flash_io0(flash_io0),
.flash_io1(flash_io1),
// SoC Core Interface
.porb_h(porb_h_buf),
.porb_h(porb_h),
.por(por_l_buf),
.resetb_core_h(rstb_h),
.clock_core(clock_core),
@ -472,6 +472,10 @@ module caravel (
wire clk_passthru;
wire resetn_passthru;
// NC passthru signal porb_h
wire porb_h_in_nc;
wire porb_h_out_nc;
mgmt_core_wrapper soc (
`ifdef USE_POWER_PINS
.VPWR(vccd_core),
@ -489,8 +493,8 @@ module caravel (
.serial_data_2_out(mprj_io_loader_data_2_buf),
.rstb_l_in(rstb_l),
.rstb_l_out(rstb_l_buf),
.porb_h_in(porb_h),
.porb_h_out(porb_h_buf),
.porb_h_in(porb_h_in_nc),
.porb_h_out(porb_h_out_nc),
.por_l_in(por_l),
.por_l_out(por_l_buf),