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cocotb - skip write and read from xfer 

because the write reg is diffrent than the read one
This commit is contained in:
M0stafaRady 2022-10-25 08:00:51 -07:00
parent 83a2e0d6c2
commit 745b3e3e2c
1 changed files with 1 additions and 1 deletions
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verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
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@ -113,7 +113,7 @@ async def hk_regs_wr_spi(dut):
if address in [111,36,10]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled and 10 0xa cpu irq is self resetting
continue
# address = int(key,16)
if address in [0x69,0x6A,0x6B,0x6C,0x6D]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
if address in [0x69,0x6A,0x6B,0x6C,0x6D,0x13]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value and xfer
continue
data_in = random.getrandbits(bits_num)
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")