From 745b3e3e2cc92f32f6de8ca917714c57a7e68f30 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Tue, 25 Oct 2022 08:00:51 -0700 Subject: [PATCH] cocotb - skip write and read from xfer because the write reg is diffrent than the read one --- .../housekeeping/housekeeping_regs/housekeeping_regs_tests.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py index b5e692cf..e8af4e8b 100644 --- a/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py +++ b/verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py @@ -113,7 +113,7 @@ async def hk_regs_wr_spi(dut): if address in [111,36,10]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled and 10 0xa cpu irq is self resetting continue # address = int(key,16) - if address in [0x69,0x6A,0x6B,0x6C,0x6D]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value + if address in [0x69,0x6A,0x6B,0x6C,0x6D,0x13]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value and xfer continue data_in = random.getrandbits(bits_num) cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")