Decreased distances from pins to and gates in mgmt_protect

This commit is contained in:
mo-hosni 2022-10-27 08:20:57 -07:00
parent 39aa7ede4f
commit 2d61e593aa
9 changed files with 576930 additions and 631598 deletions

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@ -81,22 +81,24 @@ set ::env(FP_PDN_MACRO_HOOKS) "\
set ::env(FP_PDN_SKIPTRIM) 0
## Placement
set ::env(PL_TARGET_DENSITY) 0.09
set ::env(PL_TARGET_DENSITY) 0.095
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 1
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) 320
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) 25
set ::env(PL_TIME_DRIVEN) 0
set ::env(PL_ROUTABILITY_DRIVEN) 1
## Routing
set ::env(RT_MIN_LAYER) "met1"
set ::env(RT_MAX_LAYER) "met4"
set ::env(GRT_ADJUSTMENT) 0.05
set ::env(GRT_ADJUSTMENT) 0.3
set ::env(GRT_OVERFLOW_ITERS) 280
set ::env(GRT_ALLOW_CONGESTION) 1
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 1
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) 320
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) 250
## prevent routing near the PDN to prevent DRCs at top-level
set ::env(GRT_OBS) "met4 60.970 0.000 63.870 160.000, \
@ -197,7 +199,7 @@ set ::env(MAGIC_EXT_USE_GDS) 0
set ::env(RSZ_DONT_TOUCH_RX) {la_data_out_core\[.*\]|mprj_ack_i_user|mprj_dat_i_user\[.*\]|user_irq_core\[.*\]}
## Antenna
set ::env(DIODE_INSERTION_STRATEGY) 3
set ::env(DIODE_INSERTION_STRATEGY) 6
set ::env(GRT_ANT_ITERS) 50
set ::env(GRT_MAX_DIODE_INS_ITERS) 50
# set ::env(USE_ARC_ANTENNA_CHECK) 0

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@ -1,2 +1,2 @@
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
/home/hosni/My_forks/FINAL/caravel/openlane/mgmt_protect,mgmt_protect,22_10_16_02_43,flow completed,0h23m12s0ms,0h17m25s0ms,-2.0,0.3392,-1,2.25,1430.66,-1,0,0,0,0,0,0,9,-1,12,-1,-1,812932,51073,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,0.0,730722606.0,0.0,61.78,17.47,35.74,2.78,-1,176,2014,48,1886,0,0,0,921,333,0,0,0,0,0,0,0,1088,626,1,194,4525,0,4719,309717.04319999996,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,10,50,1,527.160,36.720,0.09,0.05,sky130_fd_sc_hd,3
/home/hosni/mgmt_protect/caravel/openlane/mgmt_protect,mgmt_protect,22_10_23_08_16,flow completed,0h10m3s0ms,0h4m14s0ms,-2.0,0.3392,-1,2.25,1540.5,-1,0,0,0,0,0,0,9,-1,8,-1,-1,835520,46970,0.0,-0.02,0.0,-0.06,0.0,0.0,-0.12,0.0,-0.3,0.0,720847043.0,0.0,74.97,43.04,62.33,11.56,-1,176,2014,48,1886,0,0,0,921,333,0,0,0,0,0,0,0,1088,626,1,194,4525,0,4719,309717.04319999996,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10,AREA 0,10,50,1,527.160,36.720,0.095,0.3,sky130_fd_sc_hd,3

1 design design_name config flow_status total_runtime routed_runtime (Cell/mm^2)/Core_Util DIEAREA_mm^2 CellPer_mm^2 OpenDP_Util Peak_Memory_Usage_MB cell_count tritonRoute_violations Short_violations MetSpc_violations OffGrid_violations MinHole_violations Other_violations Magic_violations antenna_violations lvs_total_errors cvc_total_errors klayout_violations wire_length vias wns pl_wns optimized_wns fastroute_wns spef_wns tns pl_tns optimized_tns fastroute_tns spef_tns HPWL routing_layer1_pct routing_layer2_pct routing_layer3_pct routing_layer4_pct routing_layer5_pct routing_layer6_pct wires_count wire_bits public_wires_count public_wire_bits memories_count memory_bits processes_count cells_pre_abc AND DFF NAND NOR OR XOR XNOR MUX inputs outputs level EndCaps TapCells Diodes Total_Physical_Cells CoreArea_um^2 power_slowest_internal_uW power_slowest_switching_uW power_slowest_leakage_uW power_typical_internal_uW power_typical_switching_uW power_typical_leakage_uW power_fastest_internal_uW power_fastest_switching_uW power_fastest_leakage_uW critical_path_ns suggested_clock_period suggested_clock_frequency CLOCK_PERIOD SYNTH_STRATEGY SYNTH_MAX_FANOUT FP_CORE_UTIL FP_ASPECT_RATIO FP_PDN_VPITCH FP_PDN_HPITCH PL_TARGET_DENSITY GRT_ADJUSTMENT STD_CELL_LIBRARY DIODE_INSERTION_STRATEGY
2 /home/hosni/My_forks/FINAL/caravel/openlane/mgmt_protect /home/hosni/mgmt_protect/caravel/openlane/mgmt_protect mgmt_protect 22_10_16_02_43 22_10_23_08_16 flow completed 0h23m12s0ms 0h10m3s0ms 0h17m25s0ms 0h4m14s0ms -2.0 0.3392 -1 2.25 1430.66 1540.5 -1 0 0 0 0 0 0 9 -1 12 8 -1 -1 812932 835520 51073 46970 0.0 0.0 -0.02 0.0 0.0 -0.06 0.0 0.0 0.0 -0.12 0.0 0.0 -0.3 0.0 730722606.0 720847043.0 0.0 61.78 74.97 17.47 43.04 35.74 62.33 2.78 11.56 -1 176 2014 48 1886 0 0 0 921 333 0 0 0 0 0 0 0 1088 626 1 194 4525 0 4719 309717.04319999996 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 10.0 100.0 10 AREA 0 10 50 1 527.160 36.720 0.09 0.095 0.05 0.3 sky130_fd_sc_hd 3

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