cocotb - Adding cpu_reset test

verilog/dv/cocotb/caravel_tests.py

@@ -45,7 +45,7 @@ from tests.uart.uart import *
 from tests.spi_master.spi_master import *
 from tests.logicAnalyzer.la import *
 from tests.debug.debug import *
-
+from tests.cpu.cpu_reset import *
 
 # archive tests
 @cocotb.test()

verilog/dv/cocotb/tests.json

@@ -344,6 +344,12 @@
             "GL":[],
             "GL_SDF":[],
             "description":"try housekeeping spi Write and Read in n-byte mode "}
+        ,"cpu_reset" :{"level":3, 
+            "SW":true,
+            "RTL":["r_rtl","nightly","weekly","tape_out"],
+            "GL":["r_gl","nightly","weekly","tape_out"],
+            "GL_SDF":["r_sdf","weekly","tape_out"],
+            "description":"test cpu reset register inside the housekeeping "}
 
     }
 }

verilog/dv/cocotb/tests/cpu/cpu_reset.c

@@ -0,0 +1,18 @@
+#include <defs.h>
+#include <stub.c>
+
+// Empty C code
+
+void main()
+{
+    reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
+    reg_debug_1  = 0x0;
+    reg_debug_1  = 0x1;
+    reg_debug_1  = 0x2;
+    reg_debug_1  = 0x3;
+    reg_debug_1  = 0x4;
+    reg_debug_1  = 0x5;
+    while(reg_debug_2 == 0x0);
+    reg_hkspi_reset = 1;
+   
+}

verilog/dv/cocotb/tests/cpu/cpu_reset.py

@@ -0,0 +1,67 @@
+import random
+import cocotb
+from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
+import cocotb.log
+from interfaces.cpu import RiskV
+from interfaces.defsParser import Regs
+from cocotb.result import TestSuccess
+from tests.common_functions.test_functions import *
+from tests.bitbang.bitbang_functions import *
+from interfaces.caravel import GPIO_MODE
+from tests.housekeeping.housekeeping_spi.spi_access_functions import *
+
+reg = Regs()
+@cocotb.test()
+@repot_test
+async def cpu_reset(dut):
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=34823)
+    cpu = RiskV(dut)
+    cpu.cpu_force_reset()
+    cpu.cpu_release_reset()
+    cocotb.log.info(f"[TEST] Start cpu_reset test")   
+    # wait for CPU to write 5 at debug_reg1
+    while True: 
+        if cpu.read_debug_reg1() == 5:
+            cocotb.log.info("[TEST] debug reg 1 = 5" )
+            break
+        await ClockCycles(caravelEnv.clk,1) 
+    
+    # put the cpu under reset using spi 
+    cocotb.log.info("[TEST] asserting cpu reset register using SPI")
+    await write_reg_spi(caravelEnv,0xb,1)
+
+    await ClockCycles(caravelEnv.clk,1000) 
+    if cpu.read_debug_reg1() == 0:
+        cocotb.log.info("[TEST] asserting cpu reset register using SPI successfully rest the cpu")
+    else: 
+        cocotb.log.error("[TEST] asserting  cpu reset register using SPI successfully doesn't rest the cpu")
+
+    cocotb.log.info("[TEST] deasserting cpu reset register using SPI")
+    await write_reg_spi(caravelEnv,0xb,0)
+    watchdog = 12000
+    while True: 
+        if cpu.read_debug_reg1() == 5:
+            cocotb.log.info("[TEST] deasserting cpu reset register using SPI  wakes the cpu up" )
+            break
+        watchdog -=1
+        if watchdog <0: 
+            cocotb.log.error("[TEST] deasserting cpu reset register using SPI doesn't wake the cpu up" )
+            break
+
+        await ClockCycles(caravelEnv.clk,1) 
+
+    cocotb.log.info("[TEST] asserting cpu reset register using firmware")
+    cpu.write_debug_reg2_backdoor(0xAA)
+    await ClockCycles(caravelEnv.clk,10000) 
+
+    watchdog = 8000
+    while True: 
+        if cpu.read_debug_reg1() == 0:
+            cocotb.log.info("[TEST] asserting cpu reset register using firmware successfully rest the cpu" )
+            break
+        watchdog -=1
+        if watchdog <0: 
+            cocotb.log.error("[TEST] asserting  cpu reset register using firmware successfully doesn't rest the cpu" )
+            break
+
+    await ClockCycles(caravelEnv.clk,100)