cocotb - Fix timeout of all tests

verilog/dv/cocotb/tests/bitbang/bitbang_tests.py

@@ -14,7 +14,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def bitbang_no_cpu_all_o(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=10206)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=9373)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_OUTPUT.value) 
@@ -129,7 +129,7 @@ async def bitbang_no_cpu_all_o(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_no_cpu_all_i(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=8005)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=7351)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     await cpu.drive_data2address(reg.get_addr('reg_mprj_io_37'),GPIO_MODE.GPIO_MODE_MGMT_STD_INPUT.value) 

verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py

@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_o(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=2075459)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1842534)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -57,7 +57,7 @@ async def bitbang_cpu_all_o(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_10(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=1581680)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1452270)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -104,7 +104,7 @@ def shift(gpio,shift_type):
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_01(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=2863378)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1452269)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -131,7 +131,7 @@ async def bitbang_cpu_all_01(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_0011(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=5963970)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1402860)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -158,7 +158,7 @@ async def bitbang_cpu_all_0011(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_1100(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=5962067)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1402426)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -214,7 +214,7 @@ def shift_2(gpio,shift_type):
 @cocotb.test()
 @repot_test
 async def bitbang_cpu_all_i(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=1691295)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1641382)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -264,7 +264,7 @@ async def bitbang_cpu_all_i(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_spi_o(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=2639757)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=294252)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -329,7 +329,7 @@ async def bitbang_spi_o(dut):
 @cocotb.test()
 @repot_test
 async def bitbang_spi_i(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=11156703)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=55417)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/cpu/cpu_stress.py

@@ -14,7 +14,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def cpu_stress(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=1492541)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1377432)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/debug/debug.py

@@ -19,7 +19,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def debug(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=33840)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=31011)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/gpio/gpio.py

@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def gpio_all_o(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=586652)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=538624)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -156,7 +156,7 @@ async def gpio_all_i(dut):
 @cocotb.test()
 @repot_test
 async def gpio_all_i_pu(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=54138,num_error=2000)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -258,7 +258,7 @@ async def gpio_all_i_pu(dut):
 @cocotb.test()
 @repot_test
 async def gpio_all_i_pd(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=54138,num_error=2000)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/gpio/gpio_user.py

@@ -73,7 +73,7 @@ async def gpio_all_o_user(dut):
 @cocotb.test()
 @repot_test
 async def gpio_all_i_user(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=56694)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=498255)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -155,7 +155,7 @@ async def gpio_all_i_user(dut):
 @cocotb.test()
 @repot_test
 async def gpio_all_i_pu_user(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=56875,num_error=2000)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -257,7 +257,7 @@ async def gpio_all_i_pu_user(dut):
 @cocotb.test()
 @repot_test
 async def gpio_all_i_pd_user(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=58961,num_error=2000)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=54138,num_error=2000)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -361,7 +361,7 @@ async def gpio_all_i_pd_user(dut):
 @cocotb.test()
 @repot_test
 async def gpio_all_bidir_user(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=290455)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=266662)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/housekeeping/general/pll.py

@@ -16,7 +16,7 @@ user_clock = 0
 @cocotb.test()
 @repot_test
 async def pll(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=47279)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py

@@ -19,7 +19,7 @@ core_clock = 0
 @cocotb.test()
 @repot_test
 async def clock_redirect(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=13060)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=13052)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -92,7 +92,7 @@ async def calculate_clk_period(clk,name):
 @cocotb.test()
 @repot_test
 async def hk_disable(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=12409)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=11393)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py

@@ -18,7 +18,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def hk_regs_wr_wb(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=700,num_error=INFINITY)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=611,num_error=INFINITY)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     with open('wb_models/housekeepingWB/HK_regs.json') as f:
@@ -70,7 +70,7 @@ async def hk_regs_wr_wb(dut):
 @cocotb.test()
 @repot_test
 async def hk_regs_wr_wb_cpu(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=198243,num_error=INFINITY)    
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=182983,num_error=INFINITY)    
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -98,7 +98,7 @@ async def hk_regs_wr_wb_cpu(dut):
 @cocotb.test()
 @repot_test
 async def hk_regs_wr_spi(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1851,num_error=INFINITY)
 
     with open('wb_models/housekeepingWB/HK_regs.json') as f:
         regs = json.load(f)
@@ -157,7 +157,7 @@ async def hk_regs_wr_spi(dut):
 @cocotb.test()
 @repot_test
 async def hk_regs_rst_spi(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=100000,num_error=INFINITY)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=2879,num_error=INFINITY)
 
     with open('wb_models/housekeepingWB/HK_regs.json') as f:
         regs = json.load(f)

verilog/dv/cocotb/tests/housekeeping/housekeeping_spi/user_pass_thru.py

@@ -17,7 +17,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def user_pass_thru_rd(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=14833)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=13771)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/irq/IRQ_external.py

@@ -17,7 +17,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def IRQ_external(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=164360)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=155225)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/irq/IRQ_timer.py

@@ -14,7 +14,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def IRQ_timer(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=166519)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=152854)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/irq/IRQ_uart.py

@@ -21,7 +21,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def IRQ_uart(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=18613481)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=318039)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/logicAnalyzer/la.py

@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def la(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=67415)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/mem/mem_stress.py

@@ -13,7 +13,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def mem_dff2(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=1426536)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1309819)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -38,7 +38,7 @@ async def mem_dff2(dut):
 @cocotb.test()
 @repot_test
 async def mem_dff(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=2378120)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=2096205)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/mgmt_gpio/mgmt_gpio.py

@@ -15,7 +15,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def mgmt_gpio_out(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=99562)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=91385)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -63,7 +63,7 @@ async def mgmt_gpio_out(dut):
 @cocotb.test()
 @repot_test
 async def mgmt_gpio_in(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=326525)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=277033)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -112,11 +112,11 @@ async def mgmt_gpio_in(dut):
 @cocotb.test()
 @repot_test
 async def mgmt_gpio_bidir(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=243058)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=94697)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
-    cocotb.log.info(f"[TEST] Start mgmt_gpio_in test")  
+    cocotb.log.info(f"[TEST] Start mgmt_gpio_bidir test")  
     phases_fails = 3
     phases_passes = 0 
     pass_list = (0x1B,0x2B,0xFF)

verilog/dv/cocotb/tests/spi_master/spi_master.py

@@ -22,7 +22,7 @@ async def spi_master_rd(dut):
     the method of testing used can't work if 2 addresses Consecutive have the same address
     """
 
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=213888)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -62,7 +62,7 @@ async def spi_master_temp(dut):
     
     the method of testing used can't work if 2 addresses Consecutive have the same address
     """
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=214842)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=39554)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/timer/timer.py

@@ -14,7 +14,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def timer0_oneshot(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=1114136)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=1023545)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -56,7 +56,7 @@ async def timer0_oneshot(dut):
 @cocotb.test()
 @repot_test
 async def timer0_periodic(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=58257)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=52016)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()

verilog/dv/cocotb/tests/uart/uart.py

@@ -19,7 +19,7 @@ reg = Regs()
 @cocotb.test()
 @repot_test
 async def uart_tx(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=375862)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=346140)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -62,7 +62,7 @@ async def start_of_tx(caravelEnv):
 @cocotb.test()
 @repot_test
 async def uart_rx(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=104029)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=98315)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()
@@ -132,7 +132,7 @@ async def uart_check_char_recieved(caravelEnv,cpu):
 @cocotb.test()
 @repot_test
 async def uart_loopback(dut):
-    caravelEnv,clock = await test_configure(dut,timeout_cycles=216756)
+    caravelEnv,clock = await test_configure(dut,timeout_cycles=199021)
     cpu = RiskV(dut)
     cpu.cpu_force_reset()
     cpu.cpu_release_reset()