riscv
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caravel
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521 Commits

Author SHA1 Message Date
D. Mitch Bailey 999d5e2311 Fixed verilog instance name and ports. 2024-09-01 08:23:15 -07:00
David Lindley d53ed92620 Updated mag files by swapping decap_12 cells with fill_4 and fill_8. Modified the verilog/gl files to match. 2024-08-29 17:22:17 -07:00
Jeff DiCorpo cc1cd7f776
Merge pull request #498 from efabless/remove_cocotb 
remove cocotb directory since it is moved under other repos
 2023-10-23 08:00:35 -07:00
Jeff DiCorpo 610a874a82
Merge branch 'main' into remove_depency_over_power 2023-10-23 07:50:12 -07:00
Jeff DiCorpo d42e78e3dd
Merge pull request #491 from efabless/fix_openframe_netlists 
Modified the verilog/rtl/openframe_netlists.v.
 2023-10-23 07:47:47 -07:00
Jeff DiCorpo eab35f8af3
Merge pull request #504 from efabless/cocotb 
update cocotb top rtl to work with cheetah soc
 2023-10-23 07:46:16 -07:00
Tim Edwards 4cd9d9cf2a Added pins "vddio" and "vssio" to the openframe and openframe project 
wrapper RTL netlists and and openframe project wrapper GL netlist.
 2023-10-18 12:47:56 -04:00
M0stafaRady 6b5829181a
Merge pull request #506 from efabless/main 
merge from main to cocotb
 2023-10-03 10:02:58 +03:00
Tim Edwards 7bfab382d8 After updating from the PR that adds the gate level chip_io_openframe.v, 
modified it so that it matches the modified chip_io_openframe layout
in this PR (namely, the GPIO "_wrapped" pads are replaced with the
equivalent non-wrapped base cells).
 2023-09-25 20:10:37 -04:00
R. Timothy Edwards 2288c7f8d7
Merge branch 'main' into fix_openframe_wrapper_interface 2023-09-25 19:41:30 -04:00
Tim Edwards 31c8f54f24 Modified the openframe padframe so that the GPIO "wrapped" 
cells are replaced with the base cells.  Routing to pins
is instead done in the "gpio_connects" cells while
improving on the original routing (fewer cross-overs,
multiple vias per contact, wider buses for the analog
signals).  Made small adjustments to many of the openframe
wrapper pins to keep them all on a 10nm grid.  Moved the
connections previously from the "wrapped" GPIO cell back
from the openframe project border, so that the border can
be clear of all blockages.  Added the DEF file of the
wrapper (previously only in the openframe example repo)
to the def/ directory.  Note:  The modified LVS scripts
depend on the gate-level netlists of the frame, which
have been committed in a prior pull request.  This pull
request does not conflict with those files.
 2023-09-25 19:26:09 -04:00
Jeff DiCorpo 978fa08023
Merge pull request #502 from efabless/openframe-lvs 
Added `caravel_openframe.v` and `chip_io_openframe.v` gl netlists
 2023-09-25 10:57:29 -07:00
mo-hosni f5199a7475 add a gate-level for `chip_io_openframe` 2023-09-24 17:10:34 +03:00
M0stafaRady 0e3b9dded8
remove cocotb directory since it is moved under other repos 2023-09-19 23:08:03 +03:00
mo-hosni cee0f31d91 add gate-level netlist for `caravel_openframe` 2023-09-18 16:59:55 +03:00
M0stafaRady 0848d6b8f5 Remove includes and add define macro to make it possible for new project to add logic 2023-09-13 06:20:15 -07:00
Tim Edwards 4a84427ec8 Modified the verilog/rtl/openframe_netlists.v. 
This file indicates which verilog files to include for openframe
simulations.  Noted that there were references in the file to
GL versions of user_id_programming.v, chip_io_openframe.v, and
caravel_openframe.v.  All three of these are already structural
verilog and do not have versions in the gl/ directory.
 2023-08-29 20:54:36 -04:00
M0stafaRady 58a568c4fe
remove duplicate declaration from caravan_core.v 2023-08-23 11:35:05 +03:00
M0stafaRady 0ec7994476 update caravan netlist with correct risc-v and some missing files 2023-08-07 13:32:37 +03:00
M0stafaRady b9ee241db9
fix compilation error at caravan core caught by iverilog 2023-07-25 13:08:35 +03:00
M0stafaRady de15fea0af update toplevel_cocotb to match the latest updates to compile 1 time 2023-07-05 03:41:30 -07:00
M0stafaRady 1d99f81955 fix path to sdf files 2023-06-21 04:26:25 -07:00
M0stafaRady 33218a99ac add top level for cocotb 2023-06-18 04:18:07 -07:00
M0stafaRady e90895bca6 fix indentation 2023-06-13 00:11:33 -07:00
M0stafaRady 7414a48187 Fix power guards for caravan and openframe 2023-06-13 00:09:17 -07:00
M0stafaRady 082e52c41d Fix power guards 2023-06-12 09:28:56 -07:00
mo-hosni e2d21e5893 changed `caravel_logo`, `caravel_motto`, `copyright_block` to `caravan_logo`, `caravan_motto`, `copyright_block_a` respectively in `verilog/gl/caravan.v` to match the layout 2023-06-01 13:46:47 -07:00
Jeff DiCorpo f04c58a8c9
Merge pull request #467 from efabless/caravan-mpw9 
Caravan mpw9
 2023-06-01 10:25:33 -07:00
Passant e88f5abf4f ~ update `caravan` mag and openlane config with the `caravan` specific logo, motto, and copyright 2023-06-01 10:10:11 -07:00
Passant 1e46e15161 ~ update `caravan_core` to fix latch-up DRC violation (non MR) 2023-06-01 09:21:00 -07:00
mo-hosni e25997cc3b swapped the left `vssd` and `vccd` rings in `caravan_core` to fix an LVS issue 2023-05-30 22:33:33 -07:00
mo-hosni 0c78dbb954 Revert "reharden `caravan_core` to reduce the long wirelengths" 
This reverts commit de16ffc6b9.
 2023-05-30 04:35:59 -07:00
mo-hosni de16ffc6b9 reharden `caravan_core` to reduce the long wirelengths 2023-05-30 02:55:16 -07:00
mo-hosni e911784fb7 reharden `caravan_core` to fix LVS and timing issues 2023-05-29 20:07:08 -07:00
mo-hosni aeb0cbc45f reharden `caravan_core` to fix long wires issues 2023-05-29 02:50:45 -07:00
mo-hosni 8de897098d reharden `caravan_core`. Used a lib for the `user_analog_project_wrapper` and fixed DRCs. 2023-05-24 13:53:03 -07:00
mo-hosni fbf53572e1 reharden `housekeeping_alt` 2023-05-24 02:34:43 -07:00
mo-hosni 59cf3da287 add the analog connections in `caravan_core` GL 2023-05-24 00:42:28 -07:00
mo-hosni 3d9243e2cb update `caravan_signal_routing` to get aligned with `caravan_core` 2023-05-23 03:19:33 -07:00
mo-hosni 0c04656e52 add initial views for `caravan` 2023-05-23 03:05:18 -07:00
mo-hosni 26964d5460 add initial physical views for `caravan_core` 2023-05-23 02:16:44 -07:00
mo-hosni 3e7af79115 add `empty_macro_1` 2023-05-22 06:05:08 -07:00
mo-hosni e076718887 add `/// sta-blackbox` in the modules that will be blackboxed in STA 2023-05-22 05:52:27 -07:00
mo-hosni 6b5aa27297 harden `housekeeping_alt` that will be integrated in `caravan_core` 2023-05-22 05:38:41 -07:00
mo-hosni 5339ed15b6 Merge branch 'caravan-mpw9-PnR' of github.com:efabless/caravel into caravan-mpw9-PnR 2023-05-22 02:34:33 -07:00
mo-hosni 4086fb7130 add PnR empty macros to act as placement obstructions 2023-05-22 02:33:57 -07:00
Tim Edwards e2cc50bae3 Copied housekeeping.v to housekeeping_alt.v and extended the 
function for clock routing to include GPIO[30] and GPIO[31], for
use with the caravan chip, which does not have GPIO in locations
14 and 15.  This restores the clock monitoring capability for
caravan.  Eventually, the housekeeping_alt module should become
the only housekeeping module, extending the clock monitoring
function for caravel and allowing the same module to be used for
both caravel and caravan.
 2023-05-19 10:54:18 -04:00
M0stafaRady c5d251bc08 fix some syntax error in caravan 2023-05-17 00:23:41 -07:00
mo-hosni 1b4692cd68 add `verilog/rtl/caravan_core.v` and modified the hierarchy in `verilog/rtl/caravan.v` 2023-05-16 01:18:27 -07:00
Tim Edwards e6169aaf8c Copied files from the original pull request into a new one. Includes 
a few layout updates since the original pull request.  The openframe
design matches the user example in caravel_openframe_project.
 2023-05-08 16:29:24 -04:00