mirror of https://github.com/efabless/caravel.git
Copied files from the original pull request into a new one. Includes
a few layout updates since the original pull request. The openframe design matches the user example in caravel_openframe_project.
This commit is contained in:
Tim Edwards
parent
d4a76d33f2
commit
e6169aaf8c
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@ -0,0 +1,210 @@
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|||
magic
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||||
tech sky130A
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||||
magscale 1 2
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||||
timestamp 1682719879
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||||
<< checkpaint >>
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||||
rect -1260 -1260 718860 1038860
|
||||
<< error_p >>
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||||
rect 149223 18082 150855 18116
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||||
<< metal5 >>
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||||
rect 78440 1018512 90960 1031002
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||||
rect 129840 1018512 142360 1031002
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||||
rect 181240 1018512 193760 1031002
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||||
rect 232640 1018512 245160 1031002
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||||
rect 284240 1018512 296760 1031002
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||||
rect 334810 1018624 346978 1030788
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||||
rect 386040 1018512 398560 1031002
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||||
rect 475040 1018512 487560 1031002
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||||
rect 526440 1018512 538960 1031002
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||||
rect 577010 1018624 589178 1030788
|
||||
rect 628240 1018512 640760 1031002
|
||||
rect 6598 956440 19088 968960
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||||
rect 698512 952840 711002 965360
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||||
rect 6167 914054 19619 924934
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||||
rect 697980 909666 711432 920546
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||||
rect 6811 871210 18975 883378
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||||
rect 698512 863640 711002 876160
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||||
rect 6811 829010 18975 841178
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||||
rect 698624 819822 710788 831990
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||||
rect 6598 786640 19088 799160
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||||
rect 698512 774440 711002 786960
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||||
rect 6598 743440 19088 755960
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||||
rect 698512 729440 711002 741960
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||||
rect 6598 700240 19088 712760
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||||
rect 698512 684440 711002 696960
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||||
rect 6598 657040 19088 669560
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||||
rect 698512 639240 711002 651760
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||||
rect 6598 613840 19088 626360
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||||
rect 698512 594240 711002 606760
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||||
rect 6598 570640 19088 583160
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||||
rect 698512 549040 711002 561560
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||||
rect 6598 527440 19088 539960
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||||
rect 698624 505222 710788 517390
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||||
rect 6811 484410 18975 496578
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||||
rect 697980 461866 711432 472746
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||||
rect 6167 442854 19619 453734
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||||
rect 698624 417022 710788 429190
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||||
rect 6598 399840 19088 412360
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||||
rect 698512 371840 711002 384360
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||||
rect 6598 356640 19088 369160
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||||
rect 698512 326640 711002 339160
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||||
rect 6598 313440 19088 325960
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||||
rect 6598 270240 19088 282760
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||||
rect 698512 281640 711002 294160
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||||
rect 6598 227040 19088 239560
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||||
rect 698512 236640 711002 249160
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||||
rect 6598 183840 19088 196360
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||||
rect 698512 191440 711002 203960
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||||
rect 698512 146440 711002 158960
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||||
rect 6811 111610 18975 123778
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||||
rect 698512 101240 711002 113760
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||||
rect 6167 70054 19619 80934
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||||
rect 80222 6811 92390 18975
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||||
rect 136713 7143 144149 18309
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||||
rect 187640 6598 200160 19088
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||||
rect 243266 6167 254146 19619
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||||
rect 296240 6598 308760 19088
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||||
rect 351040 6598 363560 19088
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||||
rect 405840 6598 418360 19088
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||||
rect 460640 6598 473160 19088
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||||
rect 515440 6598 527960 19088
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rect 570422 6811 582590 18975
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rect 624222 6811 636390 18975
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use chip_io_openframe chip_io_openframe_0
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timestamp 1682718471
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transform 1 0 0 0 1 0
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box 0 0 717600 1037600
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use openframe_project_wrapper openframe_project_wrapper_0
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timestamp 1682719879
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transform 1 0 42137 0 1 42137
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box -444 -444 633770 953770
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||||
<< labels >>
|
||||
flabel metal5 s 187640 6598 200160 19088 0 FreeSans 16000 0 0 0 gpio[38]
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port 57 nsew
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flabel metal5 s 296240 6598 308760 19088 0 FreeSans 16000 0 0 0 gpio[39]
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||||
port 58 nsew
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flabel metal5 s 351040 6598 363560 19088 0 FreeSans 16000 0 0 0 gpio[40]
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port 59 nsew
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flabel metal5 s 405840 6598 418360 19088 0 FreeSans 16000 0 0 0 gpio[41]
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port 60 nsew
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||||
flabel metal5 s 460640 6598 473160 19088 0 FreeSans 16000 0 0 0 gpio[42]
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||||
port 61 nsew
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||||
flabel metal5 s 515440 6598 527960 19088 0 FreeSans 16000 0 0 0 gpio[43]
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port 62 nsew
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||||
flabel metal5 s 624222 6811 636390 18975 0 FreeSans 16000 0 0 0 vdda
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port 5 nsew
|
||||
flabel metal5 s 80222 6811 92390 18975 0 FreeSans 16000 0 0 0 vssa
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port 6 nsew
|
||||
flabel metal5 s 243266 6167 254146 19619 0 FreeSans 16000 0 0 0 vssd
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port 8 nsew
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||||
flabel metal5 s 570422 6811 582590 18975 0 FreeSans 16000 0 0 0 vssio
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port 3 nsew
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flabel metal5 s 136713 7143 144149 18309 0 FreeSans 16000 0 0 0 resetb
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port 63 nsew
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||||
flabel metal5 s 334810 1018624 346978 1030788 0 FreeSans 16000 0 0 0 vssio_2
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||||
port 4 nsew
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||||
flabel metal5 s 628240 1018512 640760 1031002 0 FreeSans 16000 0 0 0 gpio[15]
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port 34 nsew
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||||
flabel metal5 s 526440 1018512 538960 1031002 0 FreeSans 16000 0 0 0 gpio[16]
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port 35 nsew
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||||
flabel metal5 s 475040 1018512 487560 1031002 0 FreeSans 16000 0 0 0 gpio[17]
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port 36 nsew
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||||
flabel metal5 s 386040 1018512 398560 1031002 0 FreeSans 16000 0 0 0 gpio[18]
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||||
port 37 nsew
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flabel metal5 s 284240 1018512 296760 1031002 0 FreeSans 16000 0 0 0 gpio[19]
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port 38 nsew
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flabel metal5 s 232640 1018512 245160 1031002 0 FreeSans 16000 0 0 0 gpio[20]
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port 39 nsew
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flabel metal5 s 181240 1018512 193760 1031002 0 FreeSans 16000 0 0 0 gpio[21]
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port 40 nsew
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||||
flabel metal5 s 129840 1018512 142360 1031002 0 FreeSans 16000 0 0 0 gpio[22]
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port 41 nsew
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flabel metal5 s 78440 1018512 90960 1031002 0 FreeSans 16000 0 0 0 gpio[23]
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port 42 nsew
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flabel metal5 s 577010 1018624 589178 1030788 0 FreeSans 16000 0 0 0 vssa1
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port 12 nsew
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||||
flabel metal5 s 698512 684440 711002 696960 0 FreeSans 16000 0 0 0 gpio[10]
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port 29 nsew
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flabel metal5 s 698512 729440 711002 741960 0 FreeSans 16000 0 0 0 gpio[11]
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port 30 nsew
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flabel metal5 s 698512 774440 711002 786960 0 FreeSans 16000 0 0 0 gpio[12]
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port 31 nsew
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flabel metal5 s 698512 863640 711002 876160 0 FreeSans 16000 0 0 0 gpio[13]
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port 32 nsew
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flabel metal5 s 698512 146440 711002 158960 0 FreeSans 16000 0 0 0 gpio[1]
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port 20 nsew
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flabel metal5 s 698512 191440 711002 203960 0 FreeSans 16000 0 0 0 gpio[2]
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port 21 nsew
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flabel metal5 s 698512 236640 711002 249160 0 FreeSans 16000 0 0 0 gpio[3]
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port 22 nsew
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flabel metal5 s 698512 281640 711002 294160 0 FreeSans 16000 0 0 0 gpio[4]
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port 23 nsew
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flabel metal5 s 698512 326640 711002 339160 0 FreeSans 16000 0 0 0 gpio[5]
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port 24 nsew
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flabel metal5 s 698512 371840 711002 384360 0 FreeSans 16000 0 0 0 gpio[6]
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port 25 nsew
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flabel metal5 s 698512 549040 711002 561560 0 FreeSans 16000 0 0 0 gpio[7]
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port 26 nsew
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flabel metal5 s 698512 594240 711002 606760 0 FreeSans 16000 0 0 0 gpio[8]
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port 27 nsew
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flabel metal5 s 698512 639240 711002 651760 0 FreeSans 16000 0 0 0 gpio[9]
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port 28 nsew
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flabel metal5 s 697980 909666 711432 920546 0 FreeSans 16000 0 0 0 vccd1
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port 14 nsew
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flabel metal5 s 698624 819822 710788 831990 0 FreeSans 16000 0 0 0 vdda1
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port 9 nsew
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flabel metal5 s 698624 505222 710788 517390 0 FreeSans 16000 0 0 0 vdda1_2
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port 10 nsew
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flabel metal5 s 698624 417022 710788 429190 0 FreeSans 16000 0 0 0 vssa1_2
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port 12 nsew
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flabel metal5 s 697980 461866 711432 472746 0 FreeSans 16000 0 0 0 vssd1
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port 16 nsew
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flabel metal5 s 698512 101240 711002 113760 0 FreeSans 16000 0 0 0 gpio[0]
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port 19 nsew
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flabel metal5 s 698512 952840 711002 965360 0 FreeSans 16000 0 0 0 gpio[14]
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port 33 nsew
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||||
flabel metal5 s 6167 70054 19619 80934 0 FreeSans 16000 0 0 0 vccd
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port 7 nsew
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||||
flabel metal5 s 6811 111610 18975 123778 0 FreeSans 16000 0 0 0 vddio
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||||
port 1 nsew
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||||
flabel metal5 s 6811 871210 18975 883378 0 FreeSans 16000 0 0 0 vddio_2
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port 2 nsew
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flabel metal5 s 6598 613840 19088 626360 0 FreeSans 16000 0 0 0 gpio[29]
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port 48 nsew
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flabel metal5 s 6598 570640 19088 583160 0 FreeSans 16000 0 0 0 gpio[30]
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port 49 nsew
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flabel metal5 s 6598 527440 19088 539960 0 FreeSans 16000 0 0 0 gpio[31]
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port 50 nsew
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flabel metal5 s 6598 399840 19088 412360 0 FreeSans 16000 0 0 0 gpio[32]
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port 51 nsew
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flabel metal5 s 6598 356640 19088 369160 0 FreeSans 16000 0 0 0 gpio[33]
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||||
port 52 nsew
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||||
flabel metal5 s 6598 313440 19088 325960 0 FreeSans 16000 0 0 0 gpio[34]
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port 53 nsew
|
||||
flabel metal5 s 6598 270240 19088 282760 0 FreeSans 16000 0 0 0 gpio[35]
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port 54 nsew
|
||||
flabel metal5 s 6598 227040 19088 239560 0 FreeSans 16000 0 0 0 gpio[36]
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||||
port 55 nsew
|
||||
flabel metal5 s 6598 956440 19088 968960 0 FreeSans 16000 0 0 0 gpio[24]
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||||
port 43 nsew
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||||
flabel metal5 s 6598 786640 19088 799160 0 FreeSans 16000 0 0 0 gpio[25]
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||||
port 44 nsew
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||||
flabel metal5 s 6598 743440 19088 755960 0 FreeSans 16000 0 0 0 gpio[26]
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port 45 nsew
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flabel metal5 s 6598 700240 19088 712760 0 FreeSans 16000 0 0 0 gpio[27]
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||||
port 46 nsew
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||||
flabel metal5 s 6598 657040 19088 669560 0 FreeSans 16000 0 0 0 gpio[28]
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port 47 nsew
|
||||
flabel metal5 s 6167 914054 19619 924934 0 FreeSans 16000 0 0 0 vccd2
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||||
port 15 nsew
|
||||
flabel metal5 s 6811 484410 18975 496578 0 FreeSans 16000 0 0 0 vdda2
|
||||
port 2569 nsew
|
||||
flabel metal5 s 6811 829010 18975 841178 0 FreeSans 16000 0 0 0 vssa2
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||||
port 13 nsew
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||||
flabel metal5 s 6167 442854 19619 453734 0 FreeSans 16000 0 0 0 vssd2
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||||
port 17 nsew
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flabel metal5 s 6598 183840 19088 196360 0 FreeSans 16000 0 0 0 gpio[37]
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port 56 nsew
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<< properties >>
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||||
string FIXED_BBOX 0 0 717600 1037600
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<< end >>
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||||
|
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@ -0,0 +1,189 @@
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magic
|
||||
tech sky130A
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magscale 1 2
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||||
timestamp 1682718471
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||||
<< checkpaint >>
|
||||
rect 675448 118535 678028 118712
|
||||
rect 675439 118532 678037 118535
|
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rect 674512 116974 678037 118532
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rect 674130 115945 678037 116974
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||||
rect 674130 114359 677088 115945
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||||
rect 674520 103456 677088 114359
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||||
rect 674500 100854 677112 103456
|
||||
rect 674502 100852 677100 100854
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rect 674508 98629 677100 100852
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<< metal1 >>
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rect 675778 117266 675830 117272
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rect 675778 117208 675830 117214
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rect 675682 113371 675734 115709
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rect 675586 112665 675638 112671
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rect 675586 112487 675638 112493
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rect 675490 109630 675542 109636
|
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rect 675490 109452 675542 109458
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rect 675492 101631 675540 109452
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rect 675588 108347 675636 112487
|
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rect 675682 109050 675734 113199
|
||||
rect 675586 108341 675638 108347
|
||||
rect 675586 108163 675638 108169
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||||
rect 675490 101625 675542 101631
|
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rect 675490 101567 675542 101573
|
||||
rect 675492 100265 675540 101567
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rect 675588 100462 675636 108163
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rect 675586 100456 675638 100462
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rect 675586 100278 675638 100284
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rect 675588 100265 675636 100278
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rect 675682 99896 675734 108866
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rect 675780 102183 675828 117208
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rect 675778 102177 675830 102183
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rect 675778 102119 675830 102125
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rect 675780 102106 675828 102119
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<< via1 >>
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rect 675778 117214 675830 117266
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rect 675682 113199 675734 113371
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rect 675586 112493 675638 112665
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rect 675490 109458 675542 109630
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rect 675682 108866 675734 109050
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rect 675586 108169 675638 108341
|
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rect 675490 101573 675542 101625
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rect 675586 100284 675638 100456
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rect 675778 102125 675830 102177
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<< metal2 >>
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rect 675772 117214 675778 117266
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rect 675830 117264 675836 117266
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rect 676699 117264 676708 117270
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rect 675830 117216 676708 117264
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rect 675830 117214 675836 117216
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rect 676699 117210 676708 117216
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||||
rect 676768 117210 676777 117270
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||||
rect 675676 113311 675682 113371
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||||
rect 675407 113255 675682 113311
|
||||
rect 675676 113199 675682 113255
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||||
rect 675734 113311 675740 113371
|
||||
rect 675734 113255 675887 113311
|
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rect 675734 113199 675740 113255
|
||||
rect 675407 112665 675887 112667
|
||||
rect 675407 112611 675586 112665
|
||||
rect 675580 112493 675586 112611
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||||
rect 675638 112611 675887 112665
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||||
rect 675638 112493 675644 112611
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||||
rect 675407 109630 675887 109631
|
||||
rect 675407 109575 675490 109630
|
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rect 675484 109458 675490 109575
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rect 675542 109575 675887 109630
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rect 675542 109458 675548 109575
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rect 675676 108866 675682 109050
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rect 675734 108866 675740 109050
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rect 675407 108341 675887 108343
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rect 675407 108287 675586 108341
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rect 675580 108169 675586 108287
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rect 675638 108287 675887 108341
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rect 675638 108169 675644 108287
|
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rect 675762 102177 675840 102179
|
||||
rect 675762 102125 675778 102177
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||||
rect 675830 102125 675840 102177
|
||||
rect 675762 102123 675840 102125
|
||||
rect 675407 101625 675887 101627
|
||||
rect 675407 101573 675490 101625
|
||||
rect 675542 101573 675887 101625
|
||||
rect 675407 101571 675887 101573
|
||||
rect 675580 100339 675586 100456
|
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rect 675407 100284 675586 100339
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rect 675638 100339 675644 100456
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rect 675638 100284 675887 100339
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rect 675407 100283 675887 100284
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<< via2 >>
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rect 676708 117210 676768 117270
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rect 675505 115647 675730 115703
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rect 675505 115095 675730 115151
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rect 675506 114451 675731 114507
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rect 675506 113807 675731 113863
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rect 675506 111967 675731 112023
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rect 675505 111415 675730 111471
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rect 675505 110771 675730 110827
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rect 675505 110127 675730 110183
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rect 675505 107643 675730 107699
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rect 675506 107091 675731 107147
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rect 675506 106447 675731 106503
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rect 675505 105803 675730 105859
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rect 675504 105251 675729 105307
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rect 675506 104607 675731 104663
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rect 675506 103411 675731 103467
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rect 675505 102767 675730 102823
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rect 675505 100927 675730 100983
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<< metal3 >>
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rect 676708 117275 676768 117452
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rect 676703 117270 676773 117275
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rect 676703 117210 676708 117270
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rect 676768 117210 676773 117270
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rect 676703 117205 676773 117210
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rect 675407 115703 675736 115710
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rect 675407 115647 675505 115703
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rect 675730 115647 675887 115703
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rect 675407 115640 675736 115647
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rect 675407 115151 675737 115158
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rect 675407 115095 675505 115151
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rect 675730 115095 675887 115151
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rect 675407 115088 675737 115095
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rect 675407 114507 675737 114514
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rect 675407 114451 675506 114507
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rect 675731 114451 675887 114507
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rect 675407 114444 675737 114451
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rect 675407 113863 675737 113870
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rect 675407 113807 675506 113863
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rect 675731 113807 675887 113863
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rect 675407 113800 675737 113807
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rect 675407 112023 675737 112030
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rect 675407 111967 675506 112023
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rect 675731 111967 675887 112023
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rect 675407 111960 675737 111967
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rect 675407 111471 675737 111478
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rect 675407 111415 675505 111471
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rect 675730 111415 675887 111471
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rect 675407 111408 675737 111415
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rect 675407 110827 675737 110834
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rect 675407 110771 675505 110827
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rect 675730 110771 675887 110827
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rect 675407 110764 675737 110771
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rect 675407 110183 675737 110190
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rect 675407 110127 675505 110183
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rect 675730 110127 675887 110183
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rect 675407 110120 675737 110127
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rect 675407 107699 675737 107706
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rect 675407 107643 675505 107699
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rect 675730 107643 675887 107699
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rect 675407 107636 675737 107643
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rect 675407 107147 675737 107154
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rect 675407 107091 675506 107147
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rect 675731 107091 675887 107147
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rect 675407 107084 675737 107091
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rect 675407 106503 675737 106510
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rect 675407 106447 675506 106503
|
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rect 675731 106447 675887 106503
|
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rect 675407 106440 675737 106447
|
||||
rect 675407 105859 675737 105866
|
||||
rect 675407 105803 675505 105859
|
||||
rect 675730 105803 675887 105859
|
||||
rect 675407 105796 675737 105803
|
||||
rect 675406 105307 675736 105314
|
||||
rect 675406 105251 675504 105307
|
||||
rect 675729 105251 675887 105307
|
||||
rect 675406 105244 675736 105251
|
||||
rect 675407 104663 675737 104670
|
||||
rect 675407 104607 675506 104663
|
||||
rect 675731 104607 675887 104663
|
||||
rect 675407 104600 675737 104607
|
||||
rect 675407 103467 675737 103474
|
||||
rect 675407 103411 675506 103467
|
||||
rect 675731 103411 675887 103467
|
||||
rect 675407 103404 675737 103411
|
||||
rect 675407 102823 675737 102830
|
||||
rect 675407 102767 675505 102823
|
||||
rect 675730 102767 675887 102823
|
||||
rect 675407 102760 675737 102767
|
||||
rect 675407 100983 675737 100990
|
||||
rect 675407 100927 675505 100983
|
||||
rect 675730 100927 675887 100983
|
||||
rect 675407 100920 675737 100927
|
||||
<< properties >>
|
||||
string flatten true
|
||||
<< end >>
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1650914729
|
||||
timestamp 1680223961
|
||||
<< isosubstrate >>
|
||||
rect -52 7354 7222 8450
|
||||
rect -52 -62 11288 7354
|
||||
|
|
@ -41,14 +41,15 @@ rect 41 7305 6927 7435
|
|||
rect 35 6388 121 7179
|
||||
rect 3043 7022 6927 7305
|
||||
rect 7110 7322 7134 7435
|
||||
rect 7110 7201 10829 7322
|
||||
rect 7110 7235 10827 7322
|
||||
rect 7110 7201 7467 7235
|
||||
rect 7110 7022 7134 7201
|
||||
rect 3043 7005 7134 7022
|
||||
rect 2907 6728 7134 6838
|
||||
rect 2907 6388 3188 6728
|
||||
rect 35 6326 3188 6388
|
||||
rect 6990 6388 7134 6728
|
||||
rect 6990 6326 10860 6388
|
||||
rect 6990 6387 7134 6728
|
||||
rect 6990 6326 10860 6387
|
||||
rect 35 6320 3220 6326
|
||||
rect 35 6318 505 6320
|
||||
rect 35 6192 48 6318
|
||||
|
|
@ -614,23 +615,23 @@ timestamp 1606074388
|
|||
transform 1 0 5446 0 1 3098
|
||||
box -5446 -3098 5446 3098
|
||||
use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
|
||||
timestamp 1646116156
|
||||
timestamp 1679235063
|
||||
transform 1 0 8523 0 1 6404
|
||||
box -66 -43 1986 897
|
||||
use sky130_fd_sc_hvl__buf_8 sky130_fd_sc_hvl__buf_8_1
|
||||
timestamp 1646116156
|
||||
timestamp 1679235063
|
||||
transform 1 0 7477 0 1 7438
|
||||
box -66 -43 1986 897
|
||||
use sky130_fd_sc_hvl__fill_4 sky130_fd_sc_hvl__fill_4_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
|
||||
timestamp 1646116156
|
||||
timestamp 1679235063
|
||||
transform 1 0 10443 0 1 6404
|
||||
box -66 -43 450 897
|
||||
use sky130_fd_sc_hvl__inv_8 sky130_fd_sc_hvl__inv_8_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
|
||||
timestamp 1646116156
|
||||
timestamp 1679235063
|
||||
transform 1 0 9397 0 1 7438
|
||||
box -66 -43 1506 897
|
||||
use sky130_fd_sc_hvl__schmittbuf_1 sky130_fd_sc_hvl__schmittbuf_1_0 $PDKPATH/libs.ref/sky130_fd_sc_hvl/mag
|
||||
timestamp 1646116156
|
||||
timestamp 1679235063
|
||||
transform 1 0 7467 0 1 6404
|
||||
box -66 -43 1122 897
|
||||
<< labels >>
|
||||
|
|
|
|||
|
|
@ -0,0 +1,116 @@
|
|||
#!/usr/bin/env python3
|
||||
|
||||
# Generate the SPICE netlist stub entry for the openframe chip_io, to be
|
||||
# used to annotate the layout. The generated file is only needed for
|
||||
# annotation and may be removed afterwards. The script is maintained to
|
||||
# regenerate the stub file on demand.
|
||||
|
||||
with open('chip_io_openframe.spice', 'w') as ofile:
|
||||
print('* Subcircuit pin order definition for chip_io_openframe', file=ofile)
|
||||
print('.subckt chip_io_openframe', file=ofile)
|
||||
print('+ vddio_pad', file=ofile)
|
||||
print('+ vddio_pad2', file=ofile)
|
||||
print('+ vssio_pad', file=ofile)
|
||||
print('+ vssio_pad2', file=ofile)
|
||||
print('+ vccd_pad', file=ofile)
|
||||
print('+ vssd_pad', file=ofile)
|
||||
print('+ vdda_pad', file=ofile)
|
||||
print('+ vssa_pad', file=ofile)
|
||||
print('+ vdda1_pad', file=ofile)
|
||||
print('+ vdda1_pad2', file=ofile)
|
||||
print('+ vssa1_pad', file=ofile)
|
||||
print('+ vssa1_pad2', file=ofile)
|
||||
print('+ vssa2_pad', file=ofile)
|
||||
print('+ vccd1_pad', file=ofile)
|
||||
print('+ vccd2_pad', file=ofile)
|
||||
print('+ vssd1_pad', file=ofile)
|
||||
print('+ vssd2_pad', file=ofile)
|
||||
|
||||
print('+ vddio', file=ofile)
|
||||
print('+ vssio', file=ofile)
|
||||
print('+ vccd', file=ofile)
|
||||
print('+ vssd', file=ofile)
|
||||
print('+ vdda', file=ofile)
|
||||
print('+ vssa', file=ofile)
|
||||
print('+ vdda1', file=ofile)
|
||||
print('+ vdda2', file=ofile)
|
||||
print('+ vssa1', file=ofile)
|
||||
print('+ vssa2', file=ofile)
|
||||
print('+ vccd1', file=ofile)
|
||||
print('+ vccd2', file=ofile)
|
||||
print('+ vssd1', file=ofile)
|
||||
print('+ vssd2', file=ofile)
|
||||
|
||||
print('+ resetb_pad', file=ofile)
|
||||
|
||||
print('+ porb_h', file=ofile)
|
||||
print('+ porb_l', file=ofile)
|
||||
print('+ por_l', file=ofile)
|
||||
print('+ resetb_h', file=ofile)
|
||||
print('+ resetb_l', file=ofile)
|
||||
|
||||
for i in range(31, -1, -1):
|
||||
print('+ mask_rev[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_out[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_oeb[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_inp_dis[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_ib_mode_sel[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_vtrip_sel[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_slow_sel[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_holdover[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_analog_en[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_analog_sel[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_analog_pol[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_dm0[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_dm1[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_dm2[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_in[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_in_h[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_loopback_zero[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ gpio_loopback_one[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ analog_io[' + str(i) + ']', file=ofile)
|
||||
|
||||
for i in range(43, -1, -1):
|
||||
print('+ analog_noesd_io[' + str(i) + ']', file=ofile)
|
||||
|
||||
print('* No contents---stub for ordering pins in layout.', file=ofile)
|
||||
print('.ends', file=ofile)
|
||||
|
|
@ -0,0 +1,79 @@
|
|||
#!/bin/bash
|
||||
#
|
||||
# Run LVS on the Openframe padframe layout and verilog.
|
||||
# If the layout netlist does not exist, then generate it from the
|
||||
# extracted .mag layout of the caravel_openframe top level. The
|
||||
# LVS script for netgen will read both top level netlists and then
|
||||
# compare the padframe cell.
|
||||
#
|
||||
# Run this script in the mag/ directory.
|
||||
#
|
||||
echo ${PDK_ROOT:=/usr/share/pdk} > /dev/null
|
||||
echo ${PDK:=sky130A} > /dev/null
|
||||
|
||||
if [ ! -f caravel_openframe.spice ]; then
|
||||
magic -dnull -noconsole -rcfile $PDK_ROOT/$PDK/libs.tech/magic/$PDK.magicrc << EOF
|
||||
drc off
|
||||
crashbackups stop
|
||||
load caravel_openframe
|
||||
select top cell
|
||||
expand
|
||||
extract do local
|
||||
# Maybe not do parasitic extraction for LVS??
|
||||
extract no all
|
||||
extract all
|
||||
ext2spice lvs
|
||||
ext2spice
|
||||
EOF
|
||||
rm -f *.ext
|
||||
fi
|
||||
|
||||
# Set the USE_POWER_PINS definition, which is not set anywhere else.
|
||||
cat > local_defs.v << EOF
|
||||
\`define USE_POWER_PINS 1
|
||||
EOF
|
||||
|
||||
# Generate script for netgen
|
||||
|
||||
cat > netgen.tcl << EOF
|
||||
|
||||
# Load top level netlists
|
||||
|
||||
puts stdout "Reading layout netlist:"
|
||||
set circuit1 [readnet spice caravel_openframe.spice]
|
||||
puts stdout "Reading verilog and schematic netlists:"
|
||||
puts stdout "Reading SPICE netlists of I/O:"
|
||||
set circuit2 [readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/sky130_fd_io.spice]
|
||||
readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_io/spice/sky130_ef_io.spice \$circuit2
|
||||
readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_fd_sc_hd.spice \$circuit2
|
||||
readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hd/spice/sky130_ef_sc_hd__decap_12.spice \$circuit2
|
||||
readnet spice $PDK_ROOT/$PDK/libs.ref/sky130_fd_sc_hvl/spice/sky130_fd_sc_hvl.spice \$circuit2
|
||||
readnet spice ../xschem/simple_por.spice \$circuit2
|
||||
puts stdout "Reading all gate-level verilog submodules:"
|
||||
readnet verilog local_defs.v \$circuit2
|
||||
readnet verilog ../verilog/rtl/defines.v \$circuit2
|
||||
readnet verilog ../verilog/rtl/pads.v \$circuit2
|
||||
|
||||
# NOTE: __openframe_project_wrapper.v is empty.
|
||||
readnet verilog ../verilog/rtl/__openframe_project_wrapper.v \$circuit2
|
||||
readnet verilog ../verilog/gl/user_id_programming.v \$circuit2
|
||||
readnet verilog ../verilog/gl/constant_block.v \$circuit2
|
||||
readnet verilog ../verilog/gl/xres_buf.v \$circuit2
|
||||
|
||||
# ALSO NOTE: Top-level modules are in the RTL directory but are purely gate level.
|
||||
readnet verilog ../verilog/rtl/chip_io_openframe.v \$circuit2
|
||||
readnet verilog ../verilog/rtl/caravel_openframe.v \$circuit2
|
||||
puts stdout "Done reading netlists."
|
||||
|
||||
# Run LVS on the chip_io_openframe cells in layout and verilog.
|
||||
|
||||
lvs "\$circuit1 chip_io_openframe" "\$circuit2 chip_io_openframe" \
|
||||
$PDK_ROOT/$PDK/libs.tech/netgen/${PDK}_setup.tcl \
|
||||
chip_io_openframe_comp.out
|
||||
EOF
|
||||
|
||||
|
||||
export NETGEN_COLUMNS=60
|
||||
netgen -batch source netgen.tcl
|
||||
rm local_defs.v
|
||||
rm netgen.tcl
|
||||
|
|
@ -0,0 +1,148 @@
|
|||
// SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
`default_nettype none
|
||||
/*
|
||||
*-------------------------------------------------------------
|
||||
*
|
||||
* openframe_project_wrapper
|
||||
*
|
||||
* This wrapper enumerates all of the pins available to the
|
||||
* user for the user openframe project.
|
||||
*
|
||||
* Written by Tim Edwards
|
||||
* March 27, 2023
|
||||
* Efabless Corporation
|
||||
*
|
||||
*-------------------------------------------------------------
|
||||
*/
|
||||
|
||||
module openframe_project_wrapper (
|
||||
`ifdef USE_POWER_PINS
|
||||
inout vdda, // User area 0 3.3V supply
|
||||
inout vdda1, // User area 1 3.3V supply
|
||||
inout vdda2, // User area 2 3.3V supply
|
||||
inout vssa, // User area 0 analog ground
|
||||
inout vssa1, // User area 1 analog ground
|
||||
inout vssa2, // User area 2 analog ground
|
||||
inout vccd, // Common 1.8V supply
|
||||
inout vccd1, // User area 1 1.8V supply
|
||||
inout vccd2, // User area 2 1.8v supply
|
||||
inout vssd, // Common digital ground
|
||||
inout vssd1, // User area 1 digital ground
|
||||
inout vssd2, // User area 2 digital ground
|
||||
`endif
|
||||
|
||||
/* Signals exported from the frame area to the user project */
|
||||
/* The user may elect to use any of these inputs. */
|
||||
|
||||
input porb_h, // power-on reset, sense inverted, 3.3V domain
|
||||
input porb_l, // power-on reset, sense inverted, 1.8V domain
|
||||
input por_l, // power-on reset, noninverted, 1.8V domain
|
||||
input resetb_h, // master reset, sense inverted, 3.3V domain
|
||||
input resetb_l, // master reset, sense inverted, 1.8V domain
|
||||
input [31:0] mask_rev, // 32-bit user ID, 1.8V domain
|
||||
|
||||
/* GPIOs. There are 44 GPIOs (19 left, 19 right, 6 bottom). */
|
||||
/* These must be configured appropriately by the user project. */
|
||||
|
||||
/* Basic bidirectional I/O. Input gpio_in_h is in the 3.3V domain; all
|
||||
* others are in the 1.8v domain. OEB is output enable, sense inverted.
|
||||
*/
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_in,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_in_h,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_out,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_oeb,
|
||||
|
||||
/* Pad configuration. These signals are usually static values.
|
||||
* See the documentation for the sky130_fd_io__gpiov2 cell signals
|
||||
* and their use.
|
||||
*/
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_inp_dis,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_ib_mode_sel,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_vtrip_sel,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_slow_sel,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_holdover,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_analog_en,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_analog_sel,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_analog_pol,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_dm2,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_dm1,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_dm0,
|
||||
|
||||
/* These signals correct directly to the pad. Pads using analog I/O
|
||||
* connections should keep the digital input and output buffers turned
|
||||
* off. Both signals connect to the same pad. The "noesd" signal
|
||||
* is a direct connection to the pad; the other signal connects through
|
||||
* a series resistor which gives it minimal ESD protection. Both signals
|
||||
* have basic over- and under-voltage protection at the pad. These
|
||||
* signals may be expected to attenuate heavily above 50MHz.
|
||||
*/
|
||||
inout [`OPENFRAME_IO_PADS-1:0] analog_io,
|
||||
inout [`OPENFRAME_IO_PADS-1:0] analog_noesd_io,
|
||||
|
||||
/* These signals are constant one and zero in the 1.8V domain, one for
|
||||
* each GPIO pad, and can be looped back to the control signals on the
|
||||
* same GPIO pad to set a static configuration at power-up.
|
||||
*/
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_loopback_one,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_loopback_zero
|
||||
);
|
||||
|
||||
`ifdef OPENFRAME_TESTING
|
||||
openframe_example test_example (
|
||||
`ifdef USE_POWER_PINS
|
||||
.vdda(vdda),
|
||||
.vdda1(vdda1),
|
||||
.vdda2(vdda2),
|
||||
.vssa(vssa),
|
||||
.vssa1(vssa1),
|
||||
.vssa2(vssa2),
|
||||
.vccd(vccd),
|
||||
.vccd1(vccd1),
|
||||
.vccd2(vccd2),
|
||||
.vssd(vssd),
|
||||
.vssd1(vssd1),
|
||||
.vssd2(vssd2),
|
||||
`endif
|
||||
.porb_h(porb_h),
|
||||
.porb_l(porb_l),
|
||||
.por_l(por_l),
|
||||
.resetb_h(resetb_h),
|
||||
.resetb_l(resetb_l),
|
||||
.mask_rev(mask_rev),
|
||||
.gpio_in(gpio_in),
|
||||
.gpio_in_h(gpio_in_h),
|
||||
.gpio_out(gpio_out),
|
||||
.gpio_oeb(gpio_oeb),
|
||||
.gpio_inp_dis(gpio_inp_dis),
|
||||
.gpio_ib_mode_sel(gpio_ib_mode_sel),
|
||||
.gpio_vtrip_sel(gpio_vtrip_sel),
|
||||
.gpio_slow_sel(gpio_slow_sel),
|
||||
.gpio_holdover(gpio_holdover),
|
||||
.gpio_analog_en(gpio_analog_en),
|
||||
.gpio_analog_sel(gpio_analog_sel),
|
||||
.gpio_analog_pol(gpio_analog_pol),
|
||||
.gpio_dm2(gpio_dm2),
|
||||
.gpio_dm1(gpio_dm1),
|
||||
.gpio_dm0(gpio_dm0),
|
||||
.analog_io(analog_io),
|
||||
.analog_noesd_io(analog_noesd_io),
|
||||
.gpio_loopback_one(gpio_loopback_one),
|
||||
.gpio_loopback_zero(gpio_loopback_zero)
|
||||
);
|
||||
`endif
|
||||
|
||||
endmodule // openframe_project_wrapper
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,517 @@
|
|||
// SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
/* chip_io_openframe ---
|
||||
*
|
||||
* RTL verilog definition of the padframe for the open-frame version
|
||||
* of the Caravel harness chip, sky130 process
|
||||
*
|
||||
* Written by Tim Edwards
|
||||
* March 27, 2023
|
||||
*/
|
||||
|
||||
// `default_nettype none
|
||||
module chip_io_openframe #(
|
||||
parameter USER_PROJECT_ID = 32'h00000000
|
||||
) (
|
||||
// Package Pins
|
||||
inout vddio_pad, // Common padframe/ESD supply
|
||||
inout vddio_pad2,
|
||||
inout vssio_pad, // Common padframe/ESD ground
|
||||
inout vssio_pad2,
|
||||
inout vccd_pad, // Common 1.8V supply
|
||||
inout vssd_pad, // Common digital ground
|
||||
inout vdda_pad, // User area 0 3.3V supply
|
||||
inout vssa_pad, // User area 0 analog ground
|
||||
inout vdda1_pad, // User area 1 3.3V supply
|
||||
inout vdda1_pad2,
|
||||
inout vdda2_pad, // User area 2 3.3V supply
|
||||
inout vssa1_pad, // User area 1 analog ground
|
||||
inout vssa1_pad2,
|
||||
inout vssa2_pad, // User area 2 analog ground
|
||||
inout vccd1_pad, // User area 1 1.8V supply
|
||||
inout vccd2_pad, // User area 2 1.8V supply
|
||||
inout vssd1_pad, // User area 1 digital ground
|
||||
inout vssd2_pad, // User area 2 digital ground
|
||||
|
||||
// Core Side
|
||||
inout vddio, // Common padframe/ESD supply
|
||||
inout vssio, // Common padframe/ESD ground
|
||||
inout vccd, // Common 1.8V supply
|
||||
inout vssd, // Common digital ground
|
||||
inout vdda, // User area 0 3.3V supply
|
||||
inout vssa, // User area 0 analog ground
|
||||
inout vdda1, // User area 1 3.3V supply
|
||||
inout vdda2, // User area 2 3.3V supply
|
||||
inout vssa1, // User area 1 analog ground
|
||||
inout vssa2, // User area 2 analog ground
|
||||
inout vccd1, // User area 1 1.8V supply
|
||||
inout vccd2, // User area 2 1.8V supply
|
||||
inout vssd1, // User area 1 digital ground
|
||||
inout vssd2, // User area 2 digital ground
|
||||
|
||||
input resetb_pad,
|
||||
|
||||
// Chip Core Interface
|
||||
output porb_h,
|
||||
output porb_l,
|
||||
output por_l,
|
||||
output resetb_h,
|
||||
output resetb_l,
|
||||
output [31:0] mask_rev,
|
||||
|
||||
// User project IOs
|
||||
inout [`OPENFRAME_IO_PADS-1:0] gpio,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_out,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_oeb,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_inp_dis,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_ib_mode_sel,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_vtrip_sel,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_slow_sel,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_holdover,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_analog_en,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_analog_sel,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_analog_pol,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_dm0,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_dm1,
|
||||
input [`OPENFRAME_IO_PADS-1:0] gpio_dm2,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_in,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_in_h,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_loopback_zero,
|
||||
output [`OPENFRAME_IO_PADS-1:0] gpio_loopback_one,
|
||||
inout [`OPENFRAME_IO_PADS-1:0] analog_io,
|
||||
inout [`OPENFRAME_IO_PADS-1:0] analog_noesd_io
|
||||
);
|
||||
|
||||
// To be considered: Individual hold signals on all GPIO pads
|
||||
// For now, set holdh_n to 1 internally (NOTE: This is in the
|
||||
// VDDIO 3.3V domain) and set enh to porb_h for all GPIO pads.
|
||||
|
||||
wire [`OPENFRAME_IO_PADS-1:0] gpio_enh;
|
||||
|
||||
assign gpio_enh = {`OPENFRAME_IO_PADS{porb_h}};
|
||||
|
||||
// Internal bus wires
|
||||
wire analog_a, analog_b;
|
||||
wire vddio_q, vssio_q;
|
||||
|
||||
// Instantiate power and ground pads for management domain
|
||||
// 12 pads: vddio, vssio, vdda, vssa, vccd, vssd
|
||||
// One each HV and LV clamp.
|
||||
|
||||
// HV clamps connect between one HV power rail and one ground
|
||||
// LV clamps have two clamps connecting between any two LV power
|
||||
// rails and grounds, and one back-to-back diode which connects
|
||||
// between the first LV clamp ground and any other ground.
|
||||
|
||||
sky130_ef_io__vddio_hvc_clamped_pad user0_vddio_hvclamp_pad_0 (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VDDIO_PAD(vddio_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
// lies in user area 2
|
||||
sky130_ef_io__vddio_hvc_clamped_pad user0_vddio_hvclamp_pad_1 (
|
||||
`USER2_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VDDIO_PAD(vddio_pad2)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vdda_hvc_clamped_pad user0_vdda_hvclamp_pad (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VDDA_PAD(vdda_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vccd_lvc_clamped_pad user0_vccd_lvclamp_pad (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VCCD_PAD(vccd_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssio_hvc_clamped_pad user0_vssio_hvclamp_pad_0 (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSIO_PAD(vssio_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssio_hvc_clamped_pad user0_vssio_hvclamp_pad_1 (
|
||||
`USER2_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSIO_PAD(vssio_pad2)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssa_hvc_clamped_pad user0_vssa_hvclamp_pad (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSA_PAD(vssa_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssd_lvc_clamped_pad user0_vssd_lvclamp_pad (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSD_PAD(vssd_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
// Instantiate power and ground pads for user 1 domain
|
||||
// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
|
||||
|
||||
sky130_ef_io__vdda_hvc_clamped_pad user1_vdda_hvclamp_pad_0 (
|
||||
`USER1_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VDDA_PAD(vdda1_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vdda_hvc_clamped_pad user1_vdda_hvclamp_pad_1 (
|
||||
`USER1_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VDDA_PAD(vdda1_pad2)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vccd_lvc_clamped3_pad user1_vccd_lvclamp_pad (
|
||||
`USER1_ABUTMENT_PINS
|
||||
.VCCD1(vccd1),
|
||||
.VSSD1(vssd1),
|
||||
`ifndef TOP_ROUTING
|
||||
.VCCD_PAD(vccd1_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssa_hvc_clamped_pad user1_vssa_hvclamp_pad_0 (
|
||||
`USER1_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSA_PAD(vssa1_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
|
||||
sky130_ef_io__vssa_hvc_clamped_pad user1_vssa_hvclamp_pad_1 (
|
||||
`USER1_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSA_PAD(vssa1_pad2)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssd_lvc_clamped3_pad user1_vssd_lvclamp_pad (
|
||||
`USER1_ABUTMENT_PINS
|
||||
.VCCD1(vccd1),
|
||||
.VSSD1(vssd1),
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSD_PAD(vssd1_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
// Instantiate power and ground pads for user 2 domain
|
||||
// 8 pads: vdda, vssa, vccd, vssd; One each HV and LV clamp.
|
||||
|
||||
sky130_ef_io__vdda_hvc_clamped_pad user2_vdda_hvclamp_pad (
|
||||
`USER2_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VDDA_PAD(vdda2_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vccd_lvc_clamped3_pad user2_vccd_lvclamp_pad (
|
||||
`USER2_ABUTMENT_PINS
|
||||
.VCCD1(vccd2),
|
||||
.VSSD1(vssd2),
|
||||
`ifndef TOP_ROUTING
|
||||
.VCCD_PAD(vccd2_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssa_hvc_clamped_pad user2_vssa_hvclamp_pad (
|
||||
`USER2_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSA_PAD(vssa2_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
sky130_ef_io__vssd_lvc_clamped3_pad user2_vssd_lvclamp_pad (
|
||||
`USER2_ABUTMENT_PINS
|
||||
.VCCD1(vccd2),
|
||||
.VSSD1(vssd2),
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSD_PAD(vssd2_pad)
|
||||
`endif
|
||||
);
|
||||
|
||||
// Constant values in 1.8V domain to drive constant signals on GPIO pads
|
||||
// These are exported to the user project for direct loopback if needed.
|
||||
|
||||
constant_block constant_value_inst [`OPENFRAME_IO_PADS-1:0] (
|
||||
.vccd(vccd),
|
||||
.vssd(vssd),
|
||||
.one(gpio_loopback_one),
|
||||
.zero(gpio_loopback_zero)
|
||||
);
|
||||
|
||||
// One additional constant block provides the constant one value
|
||||
// for the reset pad (see below)
|
||||
|
||||
wire xres_loopback_one;
|
||||
wire xres_loopback_zero;
|
||||
|
||||
constant_block constant_value_xres_inst (
|
||||
.vccd(vccd),
|
||||
.vssd(vssd),
|
||||
.one(xres_loopback_one),
|
||||
.zero(xres_loopback_zero) // (unused)
|
||||
);
|
||||
|
||||
// Master reset pad (only digital pad not assigned as GPIO)
|
||||
|
||||
wire xresloop;
|
||||
wire xres_vss_loop;
|
||||
|
||||
sky130_fd_io__top_xres4v2 master_resetb_pad (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.PAD(resetb_pad),
|
||||
`endif
|
||||
.TIE_WEAK_HI_H(xresloop), // Loop-back connection to pad through pad_a_esd_h
|
||||
.TIE_HI_ESD(),
|
||||
.TIE_LO_ESD(xres_vss_loop),
|
||||
.PAD_A_ESD_H(xresloop),
|
||||
.XRES_H_N(resetb_h),
|
||||
.DISABLE_PULLUP_H(xres_vss_loop), // 0 = enable pull-up on reset pad
|
||||
.ENABLE_H(porb_h), // Power-on-reset
|
||||
.EN_VDDIO_SIG_H(xres_vss_loop), // No idea.
|
||||
.INP_SEL_H(xres_vss_loop), // 1 = use filt_in_h else filter the pad input
|
||||
.FILT_IN_H(xres_vss_loop), // Alternate input for glitch filter
|
||||
.PULLUP_H(xres_vss_loop), // Pullup connection for alternate filter input
|
||||
.ENABLE_VDDIO(xres_loopback_one)
|
||||
);
|
||||
|
||||
// Buffer the reset pad output to generate a signal in the 1.8V domain
|
||||
|
||||
xres_buf rstb_level (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vddio),
|
||||
.LVPWR(vccd),
|
||||
.LVGND(vssd),
|
||||
.VGND(vssio),
|
||||
`endif
|
||||
.A(resetb_h),
|
||||
.X(resetb_l)
|
||||
);
|
||||
|
||||
// Power-on-reset circuit
|
||||
|
||||
simple_por por (
|
||||
`ifdef USE_POWER_PINS
|
||||
.vdd3v3(vddio),
|
||||
.vdd1v8(vccd),
|
||||
.vss3v3(vssio),
|
||||
.vss1v8(vssd),
|
||||
`endif
|
||||
.porb_h(porb_h),
|
||||
.porb_l(porb_l),
|
||||
.por_l(por_l)
|
||||
);
|
||||
|
||||
// User ID block
|
||||
user_id_programming #(
|
||||
.USER_PROJECT_ID(USER_PROJECT_ID)
|
||||
) user_id_value (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd),
|
||||
.VGND(vssd),
|
||||
`endif
|
||||
.mask_rev(mask_rev)
|
||||
);
|
||||
|
||||
// Corner cells (These are overlay cells; it is not clear what is normally
|
||||
// supposed to go under them.)
|
||||
|
||||
sky130_ef_io__corner_pad user0_corner [1:0] (
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSIO(vssio),
|
||||
.VDDIO(vddio),
|
||||
.VDDIO_Q(vddio_q),
|
||||
.VSSIO_Q(vssio_q),
|
||||
.AMUXBUS_A(analog_a),
|
||||
.AMUXBUS_B(analog_b),
|
||||
.VSSD(vssd),
|
||||
.VSSA(vssa),
|
||||
.VSWITCH(vddio),
|
||||
.VDDA(vdda),
|
||||
.VCCD(vccd),
|
||||
.VCCHIB(vccd)
|
||||
`endif
|
||||
);
|
||||
sky130_ef_io__corner_pad user1_corner (
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSIO(vssio),
|
||||
.VDDIO(vddio),
|
||||
.VDDIO_Q(vddio_q),
|
||||
.VSSIO_Q(vssio_q),
|
||||
.AMUXBUS_A(analog_a),
|
||||
.AMUXBUS_B(analog_b),
|
||||
.VSSD(vssd),
|
||||
.VSSA(vssa1),
|
||||
.VSWITCH(vddio),
|
||||
.VDDA(vdda1),
|
||||
.VCCD(vccd),
|
||||
.VCCHIB(vccd)
|
||||
`endif
|
||||
);
|
||||
sky130_ef_io__corner_pad user2_corner (
|
||||
`ifndef TOP_ROUTING
|
||||
.VSSIO(vssio),
|
||||
.VDDIO(vddio),
|
||||
.VDDIO_Q(vddio_q),
|
||||
.VSSIO_Q(vssio_q),
|
||||
.AMUXBUS_A(analog_a),
|
||||
.AMUXBUS_B(analog_b),
|
||||
.VSSD(vssd),
|
||||
.VSSA(vssa2),
|
||||
.VSWITCH(vddio),
|
||||
.VDDA(vdda2),
|
||||
.VCCD(vccd),
|
||||
.VCCHIB(vccd)
|
||||
`endif
|
||||
);
|
||||
|
||||
wire [`OPENFRAME_IO_PADS-1:0] loop0_gpio; // Internal loopback to 3.3V domain ground
|
||||
wire [`OPENFRAME_IO_PADS-1:0] loop1_gpio; // Internal loopback to 3.3V domain power
|
||||
|
||||
/* Digital mode signal DM is the interleaved concatenation of */
|
||||
/* GPIO signals dm2, dm1, and dm0 when passed to the GPIO pad */
|
||||
/* array, so generated the concatenated signal dm_all. */
|
||||
|
||||
wire [(`OPENFRAME_IO_PADS * 3)-1:0] gpio_dm_all;
|
||||
|
||||
genvar i;
|
||||
generate
|
||||
for (i = 0; i < `OPENFRAME_IO_PADS; i = i+1) begin
|
||||
assign gpio_dm_all[(i*3) + 2] = gpio_dm2[i];
|
||||
assign gpio_dm_all[(i*3) + 1] = gpio_dm1[i];
|
||||
assign gpio_dm_all[(i*3) + 0] = gpio_dm0[i];
|
||||
end
|
||||
endgenerate
|
||||
|
||||
/* Openframe pads (right side, power domain 1) */
|
||||
|
||||
sky130_ef_io__gpiov2_pad_wrapped area1_gpio_pad [`MPRJ_IO_PADS_1 - 1:0] (
|
||||
`USER1_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.PAD(gpio[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
`endif
|
||||
.OUT(gpio_out[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.OE_N(gpio_oeb[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.HLD_H_N(loop1_gpio[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.ENABLE_H(gpio_enh[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.ENABLE_INP_H(loop0_gpio[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.ENABLE_VDDA_H(porb_h),
|
||||
.ENABLE_VSWITCH_H(loop0_gpio[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.ENABLE_VDDIO(gpio_loopback_one[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.INP_DIS(gpio_inp_dis[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.IB_MODE_SEL(gpio_ib_mode_sel[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.VTRIP_SEL(gpio_vtrip_sel[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.SLOW(gpio_slow_sel[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.HLD_OVR(gpio_holdover[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.ANALOG_EN(gpio_analog_en[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.ANALOG_SEL(gpio_analog_sel[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.ANALOG_POL(gpio_analog_pol[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.DM(gpio_dm_all[(`MPRJ_IO_PADS_1)*3 - 1:0]),
|
||||
.PAD_A_NOESD_H(analog_noesd_io[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.PAD_A_ESD_0_H(analog_io[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.PAD_A_ESD_1_H(),
|
||||
.IN(gpio_in[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.IN_H(gpio_in_h[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.TIE_HI_ESD(loop1_gpio[`MPRJ_IO_PADS_1 - 1:0]),
|
||||
.TIE_LO_ESD(loop0_gpio[`MPRJ_IO_PADS_1 - 1:0])
|
||||
);
|
||||
|
||||
/* Openframe pads (left side, power domain 2) */
|
||||
|
||||
sky130_ef_io__gpiov2_pad_wrapped area2_gpio_pad [`MPRJ_IO_PADS_2 - 1:0] (
|
||||
`USER2_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.PAD(gpio[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
`endif
|
||||
.OUT(gpio_out[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.OE_N(gpio_oeb[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.HLD_H_N(loop1_gpio[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.ENABLE_H(gpio_enh[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.ENABLE_INP_H(loop0_gpio[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.ENABLE_VDDA_H(porb_h),
|
||||
.ENABLE_VSWITCH_H(loop0_gpio[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.ENABLE_VDDIO(gpio_loopback_one[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.INP_DIS(gpio_inp_dis[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.IB_MODE_SEL(gpio_ib_mode_sel[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.VTRIP_SEL(gpio_vtrip_sel[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.SLOW(gpio_slow_sel[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.HLD_OVR(gpio_holdover[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.ANALOG_EN(gpio_analog_en[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.ANALOG_SEL(gpio_analog_sel[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.ANALOG_POL(gpio_analog_pol[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.DM(gpio_dm_all[(`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)*3 - 1:(`MPRJ_IO_PADS_1)*3]),
|
||||
.PAD_A_NOESD_H(analog_noesd_io[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.PAD_A_ESD_0_H(analog_io[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.PAD_A_ESD_1_H(),
|
||||
.IN(gpio_in[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.IN_H(gpio_in_h[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.TIE_HI_ESD(loop1_gpio[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1]),
|
||||
.TIE_LO_ESD(loop0_gpio[`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2 - 1:`MPRJ_IO_PADS_1])
|
||||
);
|
||||
|
||||
/* Openframe pads (bottom side, power domain 0) */
|
||||
|
||||
sky130_ef_io__gpiov2_pad_wrapped area0_gpio_pad [`OPENFRAME_IO_PADS - (`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2) - 1:0] (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
.PAD(gpio[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
`endif
|
||||
.OUT(gpio_out[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.OE_N(gpio_oeb[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.HLD_H_N(loop1_gpio[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.ENABLE_H(gpio_enh[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.ENABLE_INP_H(loop0_gpio[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.ENABLE_VDDA_H(porb_h),
|
||||
.ENABLE_VSWITCH_H(loop0_gpio[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.ENABLE_VDDIO(gpio_loopback_one[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.INP_DIS(gpio_inp_dis[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.IB_MODE_SEL(gpio_ib_mode_sel[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.VTRIP_SEL(gpio_vtrip_sel[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.SLOW(gpio_slow_sel[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.HLD_OVR(gpio_holdover[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.ANALOG_EN(gpio_analog_en[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.ANALOG_SEL(gpio_analog_sel[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.ANALOG_POL(gpio_analog_pol[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.DM(gpio_dm_all[(`OPENFRAME_IO_PADS)*3 - 1:(`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2)*3]),
|
||||
.PAD_A_NOESD_H(analog_noesd_io[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.PAD_A_ESD_0_H(analog_io[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.PAD_A_ESD_1_H(),
|
||||
.IN(gpio_in[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.IN_H(gpio_in_h[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.TIE_HI_ESD(loop1_gpio[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2]),
|
||||
.TIE_LO_ESD(loop0_gpio[`OPENFRAME_IO_PADS - 1:`MPRJ_IO_PADS_1 + `MPRJ_IO_PADS_2])
|
||||
);
|
||||
|
||||
endmodule
|
||||
// `default_nettype wire
|
||||
|
||||
|
|
@ -35,6 +35,9 @@
|
|||
|
||||
`define ANALOG_PADS (`ANALOG_PADS_1 + `ANALOG_PADS_2)
|
||||
|
||||
// Number of GPIO pads defined in the caravel openframe layout
|
||||
`define OPENFRAME_IO_PADS 44
|
||||
|
||||
// Size of soc_mem_synth
|
||||
|
||||
// Type and size of soc_mem
|
||||
|
|
|
|||
|
|
@ -0,0 +1,63 @@
|
|||
// SPDX-FileCopyrightText: 2020 Efabless Corporation
|
||||
//
|
||||
// Licensed under the Apache License, Version 2.0 (the "License");
|
||||
// you may not use this file except in compliance with the License.
|
||||
// You may obtain a copy of the License at
|
||||
//
|
||||
// http://www.apache.org/licenses/LICENSE-2.0
|
||||
//
|
||||
// Unless required by applicable law or agreed to in writing, software
|
||||
// distributed under the License is distributed on an "AS IS" BASIS,
|
||||
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
||||
// See the License for the specific language governing permissions and
|
||||
// limitations under the License.
|
||||
// SPDX-License-Identifier: Apache-2.0
|
||||
|
||||
`timescale 1 ns / 1 ps
|
||||
|
||||
`define UNIT_DELAY #1
|
||||
`define USE_POWER_PINS
|
||||
|
||||
`ifdef SIM
|
||||
|
||||
`include "defines.v"
|
||||
`include "user_defines.v"
|
||||
`include "pads.v"
|
||||
|
||||
/* NOTE: Need to pass the PDK root directory to iverilog with option -I */
|
||||
|
||||
`ifdef EF_STYLE
|
||||
`include "libs.ref/verilog/sky130_fd_io/sky130_fd_io.v"
|
||||
`include "libs.ref/verilog/sky130_fd_io/sky130_ef_io.v"
|
||||
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hd/primitives.v"
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hd/sky130_fd_sc_hd.v"
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hvl/primitives.v"
|
||||
`include "libs.ref/verilog/sky130_fd_sc_hvl/sky130_fd_sc_hvl.v"
|
||||
`else
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_fd_io.v"
|
||||
`include "libs.ref/sky130_fd_io/verilog/sky130_ef_io.v"
|
||||
|
||||
`include "libs.ref/sky130_fd_sc_hd/verilog/primitives.v"
|
||||
`include "libs.ref/sky130_fd_sc_hd/verilog/sky130_fd_sc_hd.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/primitives.v"
|
||||
`include "libs.ref/sky130_fd_sc_hvl/verilog/sky130_fd_sc_hvl.v"
|
||||
`endif
|
||||
|
||||
`ifdef GL
|
||||
`include "gl/user_id_programming.v"
|
||||
`include "gl/chip_io_openframe.v"
|
||||
`include "gl/constant_block.v"
|
||||
`include "gl/xres_buf.v"
|
||||
`include "gl/caravel_openframe.v"
|
||||
`else
|
||||
`include "user_id_programming.v"
|
||||
`include "chip_io_openframe.v"
|
||||
`include "constant_block.v"
|
||||
`include "xres_buf.v"
|
||||
`include "caravel_openframe.v"
|
||||
`endif
|
||||
|
||||
`include "simple_por.v"
|
||||
|
||||
`endif
|
||||
|
|
@ -1,5 +1,6 @@
|
|||
# NOTE: Hand-edited to change res_xhigh_po_0p69 resistors to res_xhigh_po resistors with W=0.69
|
||||
# because the former device does not get recognized when reading from GDS.
|
||||
* NOTE: Hand-edited to change res_xhigh_po_0p69 resistors to res_xhigh_po resistors with W=0.69
|
||||
* because the former device does not get recognized when reading from GDS. The magic view is annotated
|
||||
* so that it will extract properly.
|
||||
.subckt simple_por vdd3v3 vss3v3 porb_h porb_l por_l vdd1v8 vss1v8
|
||||
*.iopin vdd3v3
|
||||
*.iopin vss3v3
|
||||
|
|
@ -16,16 +17,16 @@ XM1 net3 net7 net5 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((n
|
|||
XM2 net2 net3 vss3v3 vss3v3 sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
|
||||
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
|
||||
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
|
||||
# XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
|
||||
XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=500 mult=1 m=1
|
||||
XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=500 mult=1 m=1
|
||||
* XR1 net4 vdd3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=500 mult=1 m=1
|
||||
XM4 net5 net6 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
|
||||
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
|
||||
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
|
||||
XM5 net3 net3 vss3v3 vss3v3 sky130_fd_pr__nfet_g5v0d10v5 L=0.8 W=14 nf=7 ad='int((nf+1)/2) * W/nf * 0.29'
|
||||
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
|
||||
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
|
||||
# XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
|
||||
XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=150 mult=1 m=1
|
||||
XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=150 mult=1 m=1
|
||||
* XR2 vss3v3 net4 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=150 mult=1 m=1
|
||||
XM7 net2 net2 net1 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
|
||||
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
|
||||
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
|
||||
|
|
@ -47,8 +48,8 @@ XM12 net8 net1 vdd3v3 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int
|
|||
XM13 net9 net2 net8 vdd3v3 sky130_fd_pr__pfet_g5v0d10v5 L=0.8 W=2 nf=1 ad='int((nf+1)/2) * W/nf * 0.29'
|
||||
+ as='int((nf+2)/2) * W/nf * 0.29' pd='2*int((nf+1)/2) * (W/nf + 0.29)' ps='2*int((nf+2)/2) * (W/nf + 0.29)'
|
||||
+ nrd='0.29 / W' nrs='0.29 / W' sa=0 sb=0 sd=0 mult=1 m=1
|
||||
# XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
|
||||
XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=25 mult=2 m=2
|
||||
XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po_0p69 L=25 mult=2 m=2
|
||||
* XR3 vss3v3 vss3v3 vss3v3 sky130_fd_pr__res_xhigh_po W=0.69 L=25 mult=2 m=2
|
||||
x2 net10 vss3v3 vss3v3 vdd3v3 vdd3v3 porb_h sky130_fd_sc_hvl__buf_8
|
||||
x3 net10 vss1v8 vss1v8 vdd1v8 vdd1v8 porb_l sky130_fd_sc_hvl__buf_8
|
||||
x4 net10 vss1v8 vss1v8 vdd1v8 vdd1v8 por_l sky130_fd_sc_hvl__inv_8
|
||||
|
|
|
|||
Loading…
Reference in New Issue