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caravel
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Merge pull request #506 from efabless/main 

merge from main to cocotb
This commit is contained in:
M0stafaRady 2023-10-03 10:02:58 +03:00 committed by GitHub
parent 312dbaea90 978fa08023
commit 6b5829181a
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9 changed files with 5031 additions and 38 deletions
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43
Makefile
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@ -50,7 +50,7 @@ LARGE_FILES_GZ_SPLIT += $(addsuffix .00.split, $(ARCHIVES))
MCW_ROOT?=$(PWD)/mgmt_core_wrapper
MCW ?=LITEX_VEXRISCV
MPW_TAG ?= mpw-9c
MPW_TAG ?= mpw-9e
PYTHON_BIN ?= python3
@ -200,6 +200,47 @@ __truck:
@cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/$(PDK) MAGTYPE=mag magic -noc -dnull -rcfile ./.magicrc $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_truck.out
### @rm $(UPRJ_ROOT)/mag/mag2gds_caravan.tcl
.PHONY: openframe
openframe: check-env uncompress uncompress-caravel
ifeq ($(FOREGROUND),1)
@echo "Running make openframe in the foreground..."
$(MAKE) -f $(CARAVEL_ROOT)/Makefile __openframe
@echo "Make openframe completed." 2>&1 | tee -a ./signoff/build/make_openframe.out
else
@echo "Running make openframe in the background..."
nohup $(MAKE) -f $(CARAVEL_ROOT)/Makefile __openframe >/dev/null 2>&1 &
tail -f signoff/build/make_openframe.out
@echo "Make openframe completed." 2>&1 | tee -a ./signoff/build/make_openframe.out
endif
__openframe:
@echo "###############################################"
@echo "Generating Caravel GDS (sources are in the 'gds' directory)"
@sleep 1
#### Runs from the CARAVEL_ROOT mag directory
@echo "\
drc off; \
crashbackups stop; \
addpath hexdigits; \
addpath $(UPRJ_ROOT)/mag; \
load openframe_project_wrapper; \
property LEFview true; \
property GDS_FILE $(UPRJ_ROOT)/gds/openframe_project_wrapper.gds; \
property GDS_START 0; \
load $(UPRJ_ROOT)/mag/user_id_programming; \
load $(UPRJ_ROOT)/mag/user_id_textblock; \
load $(CARAVEL_ROOT)/maglef/simple_por; \
load caravel_openframe -dereference; \
select top cell; \
expand; \
cif *hier write disable; \
cif *array write disable; \
gds write $(UPRJ_ROOT)/gds/caravel_openframe.gds; \
quit -noprompt;" > $(UPRJ_ROOT)/mag/mag2gds_caravel_openframe.tcl
### Runs from CARAVEL_ROOT
@mkdir -p ./signoff/build
@cd $(CARAVEL_ROOT)/mag && PDKPATH=${PDK_ROOT}/$(PDK) MAGTYPE=mag magic -noc -dnull -rcfile ${PDK_ROOT}/$(PDK)/libs.tech/magic/$(PDK).magicrc $(UPRJ_ROOT)/mag/mag2gds_caravel_openframe.tcl 2>&1 | tee $(UPRJ_ROOT)/signoff/build/make_openframe.out
.PHONY: clean
clean:
cd $(CARAVEL_ROOT)/verilog/dv/caravel/mgmt_soc/ && \

4
mag/openframe_project_wrapper.mag
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@ -3408,9 +3408,9 @@ flabel metal2 145190 -424 145246 56 0 FreeSans 400 270 0 0 gpio_in[38]
port 691 nsew
flabel metal2 147030 -424 147086 56 0 FreeSans 400 270 0 0 gpio_slow_sel[38]
port 339 nsew
flabel metal2 148870 -424 148926 56 0 FreeSans 400 270 0 0 gpio_dm0[38]
flabel metal2 148870 -424 148926 56 0 FreeSans 400 270 0 0 gpio_dm1[38]
port 559 nsew
flabel metal2 150710 -424 150766 56 0 FreeSans 400 270 0 0 gpio_dm1[38]
flabel metal2 150710 -424 150766 56 0 FreeSans 400 270 0 0 gpio_dm0[38]
port 603 nsew
flabel metal2 151354 -424 151410 56 0 FreeSans 400 270 0 0 gpio_analog_pol[38]
port 515 nsew

6
manifest
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@ -7,7 +7,7 @@
cc82a78753f5f5d0a1519bd81adbcff8a4296d91 verilog/rtl/__user_project_wrapper.v
3c8c04f53b2848dc46132cda82c614e06e56571b verilog/rtl/buff_flash_clkrst.v
14064261ec18d633a5d72b45b2347c388f2f446f verilog/rtl/caravan.v
502219ed86a5c1707bd0cf636f3b61de78f159d8 verilog/rtl/caravan_core.v
864365067a3fbb8fe3354d94d94c7b8469999850 verilog/rtl/caravan_core.v
e68fd2e085679d0f61040115fdd1d50651705d3a verilog/rtl/caravan_logo.v
d265ea6bf861e3f5c1b1b984ae057dbaed995008 verilog/rtl/caravan_motto.v
baf7cf0e8a8a712621aed75aff98198a663db43b verilog/rtl/caravan_netlists.v
@ -55,5 +55,5 @@ b9d6114a5067a04dd59cdd46fb988591c16743ce verilog/rtl/spare_logic_block.v
9178c87e3d5196fd3e6abae6fc310e1b663ade0e verilog/rtl/toplevel_cocotb.v
8f0bec01c914efe790a09ffe62bbfe0781069e35 verilog/rtl/xres_buf.v
256190717faa72005cf7656d8443c4c0693b3f78 scripts/set_user_id.py
98168b1fb6f80b196f9a05e725ec6ad99bc57ac6 scripts/generate_fill.py
9e31b1bbbb03024d02d54f9da8d42b3837abc5e5 scripts/compositor.py
731116709a44d13225170acc83cd34ff9e00fa39 scripts/generate_fill.py
dff8adfb05bedf96f86e16a18ce3cd5818d6fb78 scripts/compositor.py

7
scripts/compositor.py
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@ -147,9 +147,10 @@ if __name__ == '__main__':
keepmode = True
magpath = mag_dir_path
rcfile = magpath + '/.magicrc'
# pdk_root = os.getenv("PDK_ROOT")
# rcfile = pdk_root + '/sky130A/libs.tech/magic/sky130A.magicrc'
# rcfile = magpath + '/.magicrc'
pdk_root = os.getenv("PDK_ROOT")
pdk = os.getenv("PDK")
rcfile = pdk_root + '/' + pdk + '/libs.tech/magic/' + pdk + '.magicrc'
gdspath = gds_dir_path

11
scripts/generate_fill.py
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@ -153,9 +153,10 @@ if __name__ == '__main__':
distmode = True
magpath = user_project_path + '/mag'
rcfile = magpath + '/.magicrc'
# pdk_root = os.getenv("PDK_ROOT")
# rcfile = pdk_root + '/sky130A/libs.tech/magic/sky130A.magicrc'
# rcfile = magpath + '/.magicrc'
pdk_root = os.getenv("PDK_ROOT")
pdk = os.getenv("PDK")
rcfile = pdk_root + '/' + pdk + '/libs.tech/magic/' + pdk + '.magicrc'
if not os.path.isfile(rcfile):
rcfile = None
@ -187,12 +188,14 @@ if __name__ == '__main__':
print('gds readonly true', file=ofile)
print('gds rescale false', file=ofile)
print('gds read ../gds/' + project, file=ofile)
print('load ' + project, file=ofile)
print('select top cell', file=ofile)
print('expand', file=ofile)
if not distmode:
print('cif ostyle wafflefill(tiled)', file=ofile)
print('', file=ofile)
print('set fullbox [box values]', file=ofile)
# print('set fullbox [box values]', file=ofile)
print('set fullbox { 0 0 717600 1037600 }', file=ofile)
print('set xmax [lindex $fullbox 2]', file=ofile)
print('set xmin [lindex $fullbox 0]', file=ofile)
print('set fullwidth [expr {$xmax - $xmin}]', file=ofile)

1021
verilog/gl/caravel_openframe-example.v Normal file
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1031
verilog/gl/caravel_openframe.v Normal file
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2896
verilog/gl/chip_io_openframe.v Normal file
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50
verilog/rtl/caravan_core.v
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@ -180,28 +180,28 @@ module caravan_core (
*/
// One-bit GPIO dedicated to management SoC (outside of user control)
wire gpio_out_core;
wire gpio_in_core;
wire gpio_mode0_core;
wire gpio_mode1_core;
wire gpio_outenb_core;
wire gpio_inenb_core;
// wire gpio_out_core;
// wire gpio_in_core;
// wire gpio_mode0_core;
// wire gpio_mode1_core;
// wire gpio_outenb_core;
// wire gpio_inenb_core;
// 27 GPIO pads with full controls
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_inp_dis;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_oeb;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_ib_mode_sel;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_vtrip_sel;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_slow_sel;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_holdover;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_en;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_sel;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_pol;
wire [(`MPRJ_IO_PADS-`ANALOG_PADS)*3-1:0] mprj_io_dm;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_one;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_inp_dis;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_oeb;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_ib_mode_sel;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_vtrip_sel;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_slow_sel;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_holdover;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_en;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_sel;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_analog_pol;
// wire [(`MPRJ_IO_PADS-`ANALOG_PADS)*3-1:0] mprj_io_dm;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_in_3v3;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_out;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] mprj_io_one;
wire [7:0] mprj_io_zero;
// User Project Control (user-facing)
@ -212,15 +212,15 @@ module caravan_core (
wire [`MPRJ_IO_PADS-`ANALOG_PADS-1:0] user_io_in_3v3;
// 18 direct connections to GPIO for low-frequency, low-voltage analog
wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_analog;
wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_noesd;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_analog;
// wire [`MPRJ_IO_PADS-`ANALOG_PADS-10:0] user_gpio_noesd;
// 3 power supply ESD clamps for user applications
wire [2:0] user_clamp_high;
wire [2:0] user_clamp_low;
// wire [2:0] user_clamp_high;
// wire [2:0] user_clamp_low;
// 11 core connections to the analog pads
wire [`ANALOG_PADS-1:0] user_analog;
// wire [`ANALOG_PADS-1:0] user_analog;
/* Padframe control signals */
wire [`MPRJ_IO_PADS_1-`ANALOG_PADS_1-1:0] gpio_serial_link_1;