mirror of https://github.com/efabless/caravel.git
add initial views for `caravan`
This commit is contained in:
mo-hosni
parent
6a89a493d1
commit
0c04656e52
28331
def/caravan.def
28331
def/caravan.def
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73390
mag/caravan.mag
73390
mag/caravan.mag
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@ -14,123 +14,59 @@
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# SPDX-License-Identifier: Apache-2.0
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# User config
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set script_dir [file dirname [file normalize [info script]]]
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set ::env(DESIGN_NAME) caravan
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set ::env(STD_CELL_LIBRARY_OPT) "sky130_fd_sc_hd"
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set verilog_root $::env(CARAVEL_ROOT)/verilog/
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set lef_root $::env(CARAVEL_ROOT)/lef/
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set gds_root $::env(CARAVEL_ROOT)/gds/
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set mgmt_area_verilog_root $::env(MCW_ROOT)/verilog/
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set mgmt_area_lef_root $::env(MCW_ROOT)/lef/
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set mgmt_area_gds_root $::env(MCW_ROOT)/gds/
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set ::env(DESIGN_NAME) caravan
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set ::env(ROUTING_CORES) 2
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# Change if needed
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set ::env(VERILOG_FILES) "\
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$verilog_root/rtl/user_defines.v
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$verilog_root/rtl/caravan.v"
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$verilog_root/rtl/user_defines.v \
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/caravan.v"
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(SYNTH_READ_BLACKBOX_LIB) 0
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# defines and pads need to be first
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# order matters
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$verilog_root/rtl/defines.v
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$verilog_root/rtl/pads.v \
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$mgmt_area_verilog_root/rtl/mgmt_core_wrapper.v \
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$verilog_root/rtl/__user_analog_project_wrapper.v \
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$verilog_root/rtl/buff_flash_clkrst.v \
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$verilog_root/rtl/caravan_power_routing.v \
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$verilog_root/rtl/caravel_clocking.v \
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$verilog_root/rtl/caravan_signal_routing.v \
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$verilog_root/rtl/chip_io_alt.v \
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$verilog_root/rtl/digital_pll.v \
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$verilog_root/rtl/gpio_control_block.v \
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$verilog_root/rtl/gpio_defaults_block.v \
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$verilog_root/rtl/gpio_signal_buffering_alt.v \
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$verilog_root/rtl/housekeeping.v \
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$verilog_root/rtl/mgmt_protect.v \
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$verilog_root/rtl/simple_por.v\
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$verilog_root/rtl/spare_logic_block.v\
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$verilog_root/rtl/user_id_programming.v \
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$verilog_root/rtl/xres_buf.v \
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$verilog_root/rtl/caravan_logo.v \
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$verilog_root/rtl/caravan_motto.v \
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$verilog_root/rtl/copyright_block_a.v \
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$verilog_root/rtl/caravel_logo.v \
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$verilog_root/rtl/caravel_motto.v \
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$verilog_root/rtl/copyright_block.v \
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$verilog_root/rtl/open_source.v \
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$verilog_root/rtl/user_id_textblock.v \
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"
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/pads.v \
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$verilog_root/rtl/chip_io_alt.v \
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$verilog_root/gl/caravan_core.v"
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set ::env(EXTRA_LEFS) "\
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$lef_root/caravan_signal_routing.lef \
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$lef_root/caravan_logo-stub.lef \
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$lef_root/caravan_motto-stub.lef \
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$lef_root/copyright_block_a-stub.lef \
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$lef_root/caravel_logo-stub.lef \
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$lef_root/caravel_motto-stub.lef \
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$lef_root/copyright_block-stub.lef \
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$lef_root/open_source-stub.lef \
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$lef_root/user_id_textblock-stub.lef \
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$lef_root/buff_flash_clkrst.lef\
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$lef_root/caravan_power_routing.lef\
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$lef_root/caravel_clocking.lef \
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$lef_root/chip_io_alt.lef \
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$lef_root/digital_pll.lef \
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$lef_root/gpio_control_block.lef \
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$lef_root/gpio_defaults_block.lef \
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$lef_root/gpio_signal_buffering_alt.lef\
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$lef_root/housekeeping.lef \
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$lef_root/mgmt_protect.lef \
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$lef_root/simple_por.lef\
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$lef_root/spare_logic_block.lef\
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$lef_root/user_analog_project_wrapper.lef \
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$lef_root/user_id_programming.lef \
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$lef_root/xres_buf.lef\
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$mgmt_area_lef_root/mgmt_core_wrapper.lef \
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"
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$lef_root/chip_io_alt.lef \
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$lef_root/caravan_core.lef"
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set ::env(EXTRA_GDS_FILES) "\
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$gds_root/caravan_signal_routing.gds \
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$gds_root/caravan_logo.gds \
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$gds_root/caravan_motto.gds \
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$gds_root/copyright_block_a.gds \
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$gds_root/open_source.gds \
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$gds_root/user_id_textblock.gds \
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$gds_root/caravel_clocking.gds \
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$gds_root/chip_io_alt.gds \
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$gds_root/digital_pll.gds \
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$gds_root/gpio_control_block.gds \
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$gds_root/gpio_defaults_block.gds \
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$gds_root/housekeeping.gds \
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$gds_root/mgmt_protect.gds \
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$gds_root/simple_por.gds\
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$gds_root/user_analog_project_wrapper.gds \
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$gds_root/user_id_programming.gds \
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$gds_root/xres_buf.gds\
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$mgmt_area_gds_root/mgmt_core_wrapper.gds \
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$gds_root/buff_flash_clkrst.gds \
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$gds_root/gpio_signal_buffering_alt.gds \
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"
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$gds_root/copyright_block.gds \
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$gds_root/open_source.gds \
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$gds_root/user_id_textblock.gds \
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$gds_root/caravel_logo.gds \
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$gds_root/caravel_motto.gds \
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$gds_root/chip_io_alt.gds \
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$gds_root/caravan_core.gds"
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# # !!!
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# if { [info exists ::env(LVS_RUN_DIR)] || [info exists ::env(CONNECTIVITY_RUN)] } {
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# # if running to get a full floorplan, need the original pads due to
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# # missing pins in the abstracted version
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# set ::env(GPIO_PADS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lef/s8iom0s8/*.lef"]
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# }
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set ::env(SYNTH_TOP_LEVEL) 1
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set ::env(SYNTH_FLAT_TOP) 1
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set ::env(SYNTH_ELABORATE_ONLY) 1
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set ::env(LEC_ENABLE) 0
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set ::env(FP_SIZING) absolute
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set fd [open "$script_dir/../chip_dimensions.txt" "r"]
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set fd [open "$::env(DESIGN_DIR)/../chip_dimensions.txt" "r"]
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set ::env(DIE_AREA) [read $fd]
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close $fd
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set ::env(CELL_PAD) 0
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
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@ -138,26 +74,9 @@ set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(DIODE_INSERTION_STRATEGY) 0
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set ::env(GLB_RT_ALLOW_CONGESTION) 1
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set ::env(GLB_RT_OVERFLOW_ITERS) 50
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set ::env(GLB_RT_TILES) 30
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set ::env(GLB_RT_MINLAYER) 2
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set ::env(GLB_RT_MAXLAYER) 6
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set ::env(GRT_ALLOW_CONGESTION) 1
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set ::env(GLB_RT_ADJUSTMENT) "0"
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set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
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set ::env(GLB_RT_L2_ADJUSTMENT) "0.15"
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set ::env(GLB_RT_L3_ADJUSTMENT) "0.45"
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set ::env(GLB_RT_L4_ADJUSTMENT) "0.45"
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set ::env(GLB_RT_L5_ADJUSTMENT) "0.45"
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set ::env(GLB_RT_L6_ADJUSTMENT) "0"
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set ::env(TECH_LEF) $::env(DESIGN_DIR)/sky130_fd_sc_hd.tlef
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# set ::env(ROUTING_OPT_ITERS) 7
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# set ::env(GLB_RT_UNIDIRECTIONAL) 0
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set ::env(FILL_INSERTION) 0
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set ::env(RUN_FILL_INSERTION) 0
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# DON'T PUT CELLS ON THE TOP LEVEL
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set ::env(LVS_INSERT_POWER_PINS) 0
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@ -166,4 +85,6 @@ set ::env(MAGIC_GENERATE_LEF) 0
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set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
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set ::env(QUIT_ON_TR_DRC) 0
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set ::env(QUIT_ON_LVS_ERROR) 0
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set ::env(QUIT_ON_LVS_ERROR) 1
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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@ -1,37 +0,0 @@
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# SPDX-License-Identifier: Apache-2.0
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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## ORIGINAL FLOORPLAN FOR CONNECTIVITY INFO
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set ::env(CONNECTIVITY_RUN) 1
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prep -design $script_dir -tag caravan_lvs -overwrite
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set top_rtl $script_dir/../../verilog/rtl/caravan.v
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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verilog_elaborate
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logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v
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init_floorplan
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if { [info exists ::env(LVS_RUN_DIR)] } {
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file copy -force $::env(CURRENT_DEF) $::env(LVS_RUN_DIR)/lvs.def
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file copy -force $::env(CURRENT_NETLIST) $::env(LVS_RUN_DIR)/lvs.v
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file copy -force $::env(MERGED_LEF_UNPADDED) $::env(LVS_RUN_DIR)/lvs.lef
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} else {
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puts "Warning: LVS_RUN_DIR not defined"
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}
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@ -1,6 +1,6 @@
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# SPDX-FileCopyrightText: 2020 Efabless Corporation
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#
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# Licensed under the Apache License, Version 2.0 (the "License"),
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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@ -15,225 +15,60 @@
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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set save_path $script_dir/../..
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# FOR LVS AND CREATING PORT LABELS
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prep -design $script_dir -tag caravan_lvs -overwrite
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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verilog_elaborate
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init_floorplan
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file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
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file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
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set save_path "$script_dir/../.."
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# ACTUAL CHIP INTEGRATION
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set date [exec date "+%d_%m_%y_%H_%M"]
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set tag caravan_${date}
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prep -design $script_dir -tag $tag -overwrite
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prep -design $script_dir -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 1 -ignore_mismatches
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exec rm -rf $script_dir/runs/final
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exec ln -sf $script_dir/runs/$tag $script_dir/runs/final
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exec ln -sf $script_dir/runs/$::env(OPENLANE_RUN_TAG) $script_dir/runs/final
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file copy $script_dir/runs/caravan_lvs/tmp/merged_unpadded.lef $::env(TMP_DIR)/lvs.lef
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file copy $script_dir/runs/caravan_lvs/tmp/lvs.def $::env(TMP_DIR)/lvs.def
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file copy $script_dir/runs/caravan_lvs/tmp/lvs.v $::env(TMP_DIR)/lvs.v
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set ::env(SYNTH_DEFINES) "TOP_ROUTING"
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verilog_elaborate
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#logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v
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init_floorplan
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set mprj_x 326.540
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set mprj_y 1393.590
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set soc_x 260.170
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set soc_y 265.010
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add_macro_placement caravan_power_routing 0 0 N
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add_macro_placement caravan_signal_routing 0 0 N
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add_macro_placement user_id_textblock 481.36000 34.45000 N
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add_macro_placement copyright_block_a 747.91000 81.49000 N
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add_macro_placement open_source 1030.37000 11.68000 N
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add_macro_placement caravan_logo 1276.50000 30.16000 N
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add_macro_placement caravan_motto -272.80000 -0.26000 N
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add_macro_placement sigbuf 0 0 N
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add_macro_placement flash_clkrst_buffers 2292 238 N
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add_macro_placement padframe 0 0 N
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add_macro_placement soc $soc_x $soc_y N
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add_macro_placement housekeeping 2962.17 500.010 N
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add_macro_placement mprj $mprj_x $mprj_y N
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add_macro_placement mgmt_buffers 640.900 1160.180 N
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# add_macro_placement mgmt_buffers 1060.850 1234.090 N
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add_macro_placement rstb_level 708.550 235.440 S
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add_macro_placement user_id_value 3283.120 440.630 N
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add_macro_placement por 3250.730 234.721 MX
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add_macro_placement pll 3140.730 404.721 N
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add_macro_placement clock_ctrl 3133.820 276.420 N
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add_macro_placement spare_logic\\\[0\\\] 443.16 1162.64 N
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add_macro_placement spare_logic\\\[1\\\] 543.16 1162.64 N
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add_macro_placement spare_logic\\\[2\\\] 3204.37 1102.96 N
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add_macro_placement spare_logic\\\[3\\\] 2893.16 1162.64 N
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# west
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set west_x 38.155
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add_macro_placement "gpio_defaults_block_37" [expr $west_x + 3.6815559] [expr 1013.000 + 65] R0
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add_macro_placement "gpio_control_bidir_2\\\[2\\\]" $west_x 1013.000 R0
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add_macro_placement "gpio_defaults_block_36" [expr $west_x + 3.6815559] [expr 1229.000 + 65] R0
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add_macro_placement "gpio_control_bidir_2\\\[1\\\]" $west_x 1229.000 R0
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add_macro_placement "gpio_defaults_block_35" [expr $west_x + 3.6815559] [expr 1445.000 + 65] R0
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add_macro_placement "gpio_control_bidir_2\\\[0\\\]" $west_x 1445.000 R0
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add_macro_placement "gpio_defaults_block_34" [expr $west_x + 3.6815559] [expr 1661.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[9\\\]" $west_x 1661.000 R0
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add_macro_placement "gpio_defaults_block_33" [expr $west_x + 3.6815559] [expr 1877.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[8\\\]" $west_x 1877.000 R0
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add_macro_placement "gpio_defaults_block_32" [expr $west_x + 3.6815559] [expr 2093.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[7\\\]" $west_x 2093.000 R0
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add_macro_placement "gpio_defaults_block_31" [expr $west_x + 3.6815559] [expr 2731.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[6\\\]" $west_x 2731.000 R0
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add_macro_placement "gpio_defaults_block_30" [expr $west_x + 3.6815559] [expr 2947.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[5\\\]" $west_x 2947.000 R0
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add_macro_placement "gpio_defaults_block_29" [expr $west_x + 3.6815559] [expr 3163.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[4\\\]" $west_x 3163.000 R0
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add_macro_placement "gpio_defaults_block_28" [expr $west_x + 3.6815559] [expr 3379.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[3\\\]" $west_x 3379.000 R0
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add_macro_placement "gpio_defaults_block_27" [expr $west_x + 3.6815559] [expr 3595.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[2\\\]" $west_x 3595.000 R0
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add_macro_placement "gpio_defaults_block_26" [expr $west_x + 3.6815559] [expr 3811.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[1\\\]" $west_x 3811.000 R0
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add_macro_placement "gpio_defaults_block_25" [expr $west_x + 3.6815559] [expr 4027.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[0\\\]" $west_x 4027.000 R0
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# east
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set east_x 3381.015
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add_macro_placement "gpio_defaults_block_0" [expr $east_x+136.320042674] [expr 605 + 65] FN
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add_macro_placement "gpio_control_bidir_1\\\[0\\\]" $east_x 605.000 MY
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|
||||
add_macro_placement "gpio_defaults_block_1" [expr $east_x+136.320042674] [expr 831 + 65] FN
|
||||
add_macro_placement "gpio_control_bidir_1\\\[1\\\]" $east_x 831.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_2" [expr $east_x+136.320042674] [expr 1056 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[0\\\]" $east_x 1056.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_3" [expr $east_x+136.320042674] [expr 1282 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[1\\\]" $east_x 1282.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_4" [expr $east_x+136.320042674] [expr 1507 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[2\\\]" $east_x 1507.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_5" [expr $east_x+136.320042674] [expr 1732 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[3\\\]" $east_x 1732.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_6" [expr $east_x+136.320042674] [expr 1958 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[4\\\]" $east_x 1958.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_7" [expr $east_x+136.320042674] [expr 2399 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[5\\\]" $east_x 2399.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_8" [expr $east_x+136.320042674] [expr 2619 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[0\\\]" $east_x 2619.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_9" [expr $east_x+136.320042674] [expr 2844 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[1\\\]" $east_x 2844.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_10" [expr $east_x+136.320042674] [expr 3070 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[2\\\]" $east_x 3070.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_11" [expr $east_x+136.320042674] [expr 3295 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[3\\\]" $east_x 3295.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_12" [expr $east_x+136.320042674] [expr 3521 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[4\\\]" $east_x 3521.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_13" [expr $east_x+136.320042674] [expr 4424.000 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[5\\\]" $east_x 4424.000 MY
|
||||
add_macro_placement chip_core 211.5 210.5 N
|
||||
add_macro_placement user_id_textblock 175 35 N
|
||||
add_macro_placement copyright_block 482 85 N
|
||||
add_macro_placement open_source 768 15 N
|
||||
add_macro_placement caravel_logo 1080 25.5 N
|
||||
add_macro_placement caravel_motto 1350 -35 N
|
||||
|
||||
manual_macro_placement f
|
||||
|
||||
# modify to a different file
|
||||
remove_pins -input $::env(CURRENT_DEF)
|
||||
remove_empty_nets -input $::env(CURRENT_DEF)
|
||||
label_macro_pins \
|
||||
-lef $::env(CARAVEL_ROOT)/lef/caravan.lef \
|
||||
-netlist_def $::env(CURRENT_DEF)
|
||||
|
||||
set wrapper_obs "
|
||||
met1 326.540 1393.590 3246.54 4913.59, \
|
||||
met2 326.540 1393.590 3246.54 4913.59, \
|
||||
met3 326.540 1393.590 3246.54 4913.59, \
|
||||
met4 326.540 1393.590 3246.54 4913.59, \
|
||||
met5 326.540 1393.590 3246.54 4913.59"
|
||||
|
||||
set vssd_south_obs "
|
||||
met3 1193.19500 198.81000 1281.85000 270.56500, \
|
||||
met4 1193.19500 198.81000 1281.85000 270.56500"
|
||||
|
||||
set m4_south_obs "
|
||||
met4 934.51500 203.43000 3370.33500 271.49000, \
|
||||
met4 721.82000 264.80000 950.71500 1226.04000"
|
||||
|
||||
set vssa1_p2_east_obs "
|
||||
met4 3262.79500 2076.55000 3262.79500 2151.63000, \
|
||||
met3 3262.79500 2076.55000 3262.79500 2151.63000"
|
||||
|
||||
set vssd1_east_obs "
|
||||
met3 3269.73000 2281.14500 3269.73000 2379.18000, \
|
||||
met4 3269.73000 2281.14500 3269.73000 2379.18000"
|
||||
|
||||
|
||||
# add routing obstructions on the management area
|
||||
set mgmt_area_obs [list $soc_x $soc_y [expr $soc_x+2620] [expr $soc_y+820]]
|
||||
|
||||
set ::env(GLB_RT_OBS) "\
|
||||
met4 $mgmt_area_obs,\
|
||||
met5 $mgmt_area_obs,\
|
||||
$wrapper_obs"
|
||||
|
||||
try_catch openroad -python $::env(SCRIPTS_DIR)/add_def_obstructions.py \
|
||||
--input-def $::env(CURRENT_DEF) \
|
||||
--lef $::env(MERGED_LEF) \
|
||||
--obstructions $::env(GLB_RT_OBS) \
|
||||
--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
|
||||
|
||||
set_def [file rootname $::env(CURRENT_DEF)].obs.def
|
||||
|
||||
li1_hack_start
|
||||
global_routing
|
||||
detailed_routing
|
||||
li1_hack_end
|
||||
|
||||
label_macro_pins\
|
||||
-lef $::env(TMP_DIR)/lvs.lef\
|
||||
-netlist_def $::env(TMP_DIR)/lvs.def\
|
||||
-extra_args {-v\
|
||||
--map padframe vddio_pad vddio INOUT\
|
||||
--map padframe vssio_pad vssio INOUT\
|
||||
--map padframe vssa_pad vssa INOUT\
|
||||
--map padframe vccd_pad vccd INOUT\
|
||||
--map padframe vssd_pad vssd INOUT}
|
||||
foreach {process_corner lef ruleset} {
|
||||
min MERGED_LEF_MIN RCX_RULES_MIN
|
||||
max MERGED_LEF_MAX RCX_RULES_MAX
|
||||
nom MERGED_LEF RCX_RULES
|
||||
} {
|
||||
run_spef_extraction\
|
||||
-log $::env(signoff_logs)/parasitics_extraction.$process_corner.log\
|
||||
-rcx_lib $::env(LIB_SYNTH_COMPLETE)\
|
||||
-rcx_rules $::env($ruleset)\
|
||||
-rcx_lef $::env($lef)\
|
||||
-process_corner $process_corner \
|
||||
-save "$script_dir/$::env(DESIGN_NAME).$process_corner.spef"
|
||||
}
|
||||
|
||||
run_magic
|
||||
|
||||
save_views\
|
||||
-def_path $::env(CURRENT_DEF) \
|
||||
-gds_path $::env(magic_result_file_tag).gds \
|
||||
-mag_path $::env(magic_result_file_tag).mag \
|
||||
-verilog_path $::env(TMP_DIR)/lvs.v \
|
||||
-save_path $save_path \
|
||||
-tag caravan
|
||||
|
||||
exit
|
||||
|
||||
##saves to <RUN_DIR>/results/final
|
||||
save_final_views
|
||||
save_final_views -save_path .. -tag $::env(RUN_TAG)
|
||||
##
|
||||
calc_total_runtime
|
||||
save_state
|
||||
generate_final_summary_report
|
||||
check_timing_violations
|
||||
if { [info exists arg_values(-save_path)]\
|
||||
&& $arg_values(-save_path) != "" } {
|
||||
set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
|
||||
} else {
|
||||
set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
|
||||
}
|
||||
if {[info exists flags_map(-run_hooks)]} {
|
||||
run_post_run_hooks
|
||||
}
|
||||
|
|
|
|||
|
|
@ -0,0 +1 @@
|
|||
OpenLane 541c95953c90428a7d716cb9095e66ba2e92896d
|
||||
|
|
@ -0,0 +1 @@
|
|||
open_pdks af3485525297d5cbe93c129ea853da2d588fac41
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Final_Util,Peak_Memory_Usage_MB,synth_cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,pin_antenna_violations,net_antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,DecapCells,WelltapCells,DiodeCells,FillCells,NonPhysCells,TotalCells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,FP_ASPECT_RATIO,FP_CORE_UTIL,FP_PDN_HPITCH,FP_PDN_VPITCH,GRT_ADJUSTMENT,GRT_REPAIR_ANTENNAS,PL_TARGET_DENSITY,RUN_HEURISTIC_DIODE_INSERTION,STD_CELL_LIBRARY,SYNTH_MAX_FANOUT,SYNTH_STRATEGY
|
||||
/home/hosni/caravan/caravan-mpw9-PnR/caravel/openlane/caravan,caravan,23_05_23_02_53,flow completed,0h2m21s0ms,-1,-2.0,-1,-1,-1,-1,-1,7,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,0,0,0,7,7,18475999.948799998,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,11.0,90.9090909090909,10.0,1,50,153.18,153.6,0.3,0,0.6,0,sky130_fd_sc_hd,10,AREA 0
|
||||
|
4012
verilog/gl/caravan.v
4012
verilog/gl/caravan.v
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue