mirror of https://github.com/efabless/caravel.git
reharden caravel.
This commit is contained in:
mo-hosni
parent
9be48c6a7b
commit
25e96c9d62
31410
def/caravel.def
31410
def/caravel.def
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83870
mag/caravel.mag
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mag/caravel.mag
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@ -14,52 +14,31 @@
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# SPDX-License-Identifier: Apache-2.0
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# User config
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set ::env(DESIGN_NAME) caravel
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set ::env(ROUTING_CORES) 50
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set ::env(STD_CELL_LIBRARY_OPT) "sky130_fd_sc_hd"
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set verilog_root $::env(CARAVEL_ROOT)/verilog/
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set lef_root $::env(CARAVEL_ROOT)/lef/
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set gds_root $::env(CARAVEL_ROOT)/gds/
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set mgmt_area_verilog_root $::env(MCW_ROOT)/verilog/
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set mgmt_area_lef_root $::env(MCW_ROOT)/lef/
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set mgmt_area_gds_root $::env(MCW_ROOT)/gds/
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set ::env(DESIGN_NAME) caravel
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set ::env(ROUTING_CORES) 2
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# Change if needed
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set ::env(VERILOG_FILES) "\
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$verilog_root/rtl/user_defines.v \
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$verilog_root/rtl/caravel.v"
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$verilog_root/rtl/user_defines.v \
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/caravel.v"
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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set ::env(SYNTH_READ_BLACKBOX_LIB) 0
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set ::env(VERILOG_FILES_BLACKBOX) "\
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/pads.v \
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$verilog_root/rtl/chip_io.v \
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$verilog_root/rtl/__user_project_wrapper.v \
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$verilog_root/rtl/mgmt_protect.v \
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$verilog_root/rtl/gpio_defaults_block.v \
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$verilog_root/rtl/gpio_control_block.v \
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$verilog_root/rtl/user_id_programming.v \
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$verilog_root/rtl/housekeeping.v \
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$verilog_root/rtl/digital_pll.v \
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$verilog_root/rtl/caravel_clocking.v \
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$verilog_root/rtl/simple_por.v\
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$verilog_root/rtl/spare_logic_block.v\
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$verilog_root/rtl/xres_buf.v \
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$verilog_root/rtl/caravel_power_routing.v \
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$verilog_root/rtl/buff_flash_clkrst.v \
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$verilog_root/rtl/gpio_signal_buffering.v \
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$verilog_root/rtl/caravel_logo.v \
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$verilog_root/rtl/caravel_motto.v \
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$verilog_root/rtl/copyright_block.v \
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$verilog_root/rtl/open_source.v \
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$verilog_root/rtl/user_id_textblock.v \
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$mgmt_area_verilog_root/rtl/mgmt_core_wrapper.v \
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"
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$verilog_root/rtl/defines.v \
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$verilog_root/rtl/pads.v \
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$verilog_root/rtl/chip_io.v \
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$verilog_root/gl/caravel_core.v"
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set ::env(EXTRA_LEFS) "\
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$lef_root/caravel_logo-stub.lef \
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@ -67,23 +46,8 @@ set ::env(EXTRA_LEFS) "\
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$lef_root/copyright_block-stub.lef \
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$lef_root/open_source-stub.lef \
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$lef_root/user_id_textblock-stub.lef \
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$lef_root/caravel_power_routing.lef \
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$lef_root/chip_io.lef \
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$lef_root/user_project_wrapper.lef \
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$lef_root/mgmt_protect.lef \
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$lef_root/gpio_control_block.lef \
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$lef_root/gpio_defaults_block.lef \
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$lef_root/user_id_programming.lef \
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$lef_root/housekeeping.lef \
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$lef_root/digital_pll.lef \
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$lef_root/caravel_clocking.lef \
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$lef_root/simple_por.lef\
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$lef_root/xres_buf.lef\
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$lef_root/spare_logic_block.lef\
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$lef_root/buff_flash_clkrst.lef\
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$lef_root/gpio_signal_buffering.lef\
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$mgmt_area_lef_root/mgmt_core_wrapper.lef \
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"
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$lef_root/chip_io.lef \
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$lef_root/caravel_core.lef"
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set ::env(EXTRA_GDS_FILES) "\
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$gds_root/copyright_block.gds \
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@ -91,30 +55,10 @@ set ::env(EXTRA_GDS_FILES) "\
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$gds_root/user_id_textblock.gds \
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$gds_root/caravel_logo.gds \
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$gds_root/caravel_motto.gds \
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$gds_root/caravel_power_routing.gds \
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$gds_root/buff_flash_clkrst.gds \
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$gds_root/gpio_signal_buffering.gds \
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$gds_root/chip_io.gds \
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$gds_root/user_project_wrapper.gds \
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$gds_root/mgmt_protect.gds \
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$gds_root/gpio_control_block.gds \
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$gds_root/housekeeping.gds \
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$gds_root/digital_pll.gds \
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$gds_root/caravel_clocking.gds \
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$gds_root/simple_por.gds\
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$gds_root/xres_buf.gds\
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$mgmt_area_gds_root/mgmt_core_wrapper.gds \
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"
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$gds_root/chip_io.gds \
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$gds_root/caravel_core.gds"
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# # !!!
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# if { [info exists ::env(LVS_RUN_DIR)] || [info exists ::env(CONNECTIVITY_RUN)] } {
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# # if running to get a full floorplan, need the original pads due to
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# # missing pins in the abstracted version
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# set ::env(GPIO_PADS_LEF) [glob "$::env(PDK_ROOT)/$::env(PDK)/libs.ref/lef/s8iom0s8/*.lef"]
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# }
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set ::env(SYNTH_TOP_LEVEL) 1
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set ::env(SYNTH_FLAT_TOP) 1
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set ::env(SYNTH_ELABORATE_ONLY) 1
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set ::env(LEC_ENABLE) 0
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set ::env(FP_SIZING) absolute
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@ -123,7 +67,6 @@ set fd [open "$::env(DESIGN_DIR)/../chip_dimensions.txt" "r"]
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set ::env(DIE_AREA) [read $fd]
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close $fd
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set ::env(CELL_PAD) 0
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set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
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@ -131,33 +74,9 @@ set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(DIODE_INSERTION_STRATEGY) 0
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#set ::env(RT_MIN_LAYER) met1
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#set ::env(RT_MAX_LAYER) met5
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set ::env(GRT_ALLOW_CONGESTION) 1
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#set ::env(GLB_RT_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
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#set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
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#set ::env(GLB_RT_L3_ADJUSTMENT) "0.15"
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#set ::env(GLB_RT_L4_ADJUSTMENT) "0.15"
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#set ::env(GLB_RT_L5_ADJUSTMENT) "0.15"
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#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
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#set ::env(GLB_RT_L2_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L3_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L4_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L5_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L1_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L2_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L3_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L4_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L5_ADJUSTMENT) "0"
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#set ::env(GLB_RT_L6_ADJUSTMENT) "0"
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# set ::env(ROUTING_OPT_ITERS) 7
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set ::env(GLB_RT_UNIDIRECTIONAL) 0
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set ::env(FILL_INSERTION) 0
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set ::env(RUN_FILL_INSERTION) 0
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# DON'T PUT CELLS ON THE TOP LEVEL
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set ::env(LVS_INSERT_POWER_PINS) 0
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@ -166,19 +85,6 @@ set ::env(MAGIC_GENERATE_LEF) 0
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set ::env(QUIT_ON_ILLEGAL_OVERLAPS) 0
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set ::env(QUIT_ON_TR_DRC) 0
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set ::env(QUIT_ON_LVS_ERROR) 0
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set ::env(QUIT_ON_LVS_ERROR) 1
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#set ::env(TRACKS_INFO_FILE) $::env(DESIGN_DIR)/tracks.info
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#
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set ::env(ROUTING_OPT_ITERS) 100
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set ::env(TECH_LEF) $::env(DESIGN_DIR)/sky130_fd_sc_hd.tlef
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set ::env(GLB_RT_ADJUSTMENT) "0"
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set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
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set ::env(GLB_RT_L2_ADJUSTMENT) "0.3"
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set ::env(GLB_RT_L3_ADJUSTMENT) "0.45"
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set ::env(GLB_RT_L4_ADJUSTMENT) "0.2"
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set ::env(GLB_RT_L5_ADJUSTMENT) "0.45"
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set ::env(GLB_RT_L6_ADJUSTMENT) "0"
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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@ -15,233 +15,60 @@
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package require openlane
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set script_dir [file dirname [file normalize [info script]]]
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set save_path $script_dir/../..
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# FOR LVS AND CREATING PORT LABELS
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prep -design $script_dir -tag caravel_lvs -overwrite --verbose 2
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set ::env(SYNTH_DEFINES) "USE_POWER_PINS"
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verilog_elaborate
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set ::env(CURRENT_SDC) $::env(BASE_SDC_FILE)
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init_floorplan
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file copy -force $::env(CURRENT_DEF) $::env(TMP_DIR)/lvs.def
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file copy -force $::env(CURRENT_NETLIST) $::env(TMP_DIR)/lvs.v
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set save_path "$script_dir/../.."
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# ACTUAL CHIP INTEGRATION
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prep -design $script_dir -tag caravel -overwrite
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prep -design $script_dir -tag $::env(OPENLANE_RUN_TAG) -overwrite -verbose 1 -ignore_mismatches
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exec rm -rf $script_dir/runs/final
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exec ln -sf $script_dir/runs/$::env(OPENLANE_RUN_TAG) $script_dir/runs/final
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file copy $script_dir/runs/caravel_lvs/tmp/merged_unpadded.lef $::env(TMP_DIR)/lvs.lef
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file copy $script_dir/runs/caravel_lvs/tmp/lvs.def $::env(TMP_DIR)/lvs.def
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file copy $script_dir/runs/caravel_lvs/tmp/lvs.v $::env(TMP_DIR)/lvs.v
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set ::env(SYNTH_DEFINES) "TOP_ROUTING"
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verilog_elaborate
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#logic_equiv_check -lhs $top_rtl -rhs $::env(yosys_result_file_tag).v
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init_floorplan
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set mprj_x 326.540
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set mprj_y 1393.590
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set soc_x 260.170
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set soc_y 265.010
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add_macro_placement padframe 0 0 N
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add_macro_placement soc $soc_x $soc_y N
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add_macro_placement housekeeping 3032.170 500.010 N
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add_macro_placement mprj $mprj_x $mprj_y N
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add_macro_placement mgmt_buffers 960.900 1160.180 N
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# add_macro_placement mgmt_buffers 1060.850 1234.090 N
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add_macro_placement rstb_level 708.550 235.440 S
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add_macro_placement user_id_value 3283.120 440.630 N
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add_macro_placement por 3250.730 234.721 MX
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add_macro_placement pll 3140.730 404.721 N
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add_macro_placement spare_logic\\\[0\\\] 443.16 1162.64 N
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add_macro_placement spare_logic\\\[1\\\] 843.16 1162.64 N
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add_macro_placement spare_logic\\\[2\\\] 3204.37 1102.96 N
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add_macro_placement spare_logic\\\[3\\\] 2143.16 1162.64 N
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add_macro_placement clocking 3133.820 316.420 N
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#add_macro_placement clocking 1028.730 27.440 N
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# west
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set west_x 38.155
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add_macro_placement "gpio_control_bidir_2\\\[2\\\]" $west_x 1013.000 R0
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add_macro_placement "gpio_defaults_block_37" [expr $west_x + 3.6815559] [expr 1013.000 + 65] R0
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add_macro_placement "gpio_control_bidir_2\\\[1\\\]" $west_x 1229.000 R0
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add_macro_placement "gpio_defaults_block_36" [expr $west_x + 3.6815559] [expr 1229.000 + 65] R0
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add_macro_placement "gpio_control_bidir_2\\\[0\\\]" $west_x 1445.000 R0
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add_macro_placement "gpio_defaults_block_35" [expr $west_x + 3.6815559] [expr 1445.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[15\\\]" $west_x 1661.000 R0
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add_macro_placement "gpio_defaults_block_34" [expr $west_x + 3.6815559] [expr 1661.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[14\\\]" $west_x 1877.000 R0
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add_macro_placement "gpio_defaults_block_33" [expr $west_x + 3.6815559] [expr 1877.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[13\\\]" $west_x 2093.000 R0
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add_macro_placement "gpio_defaults_block_32" [expr $west_x + 3.6815559] [expr 2093.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[12\\\]" $west_x 2731.000 R0
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add_macro_placement "gpio_defaults_block_31" [expr $west_x + 3.6815559] [expr 2731.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[11\\\]" $west_x 2947.000 R0
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add_macro_placement "gpio_defaults_block_30" [expr $west_x + 3.6815559] [expr 2947.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[10\\\]" $west_x 3163.000 R0
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add_macro_placement "gpio_defaults_block_29" [expr $west_x + 3.6815559] [expr 3163.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[9\\\]" $west_x 3379.000 R0
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add_macro_placement "gpio_defaults_block_28" [expr $west_x + 3.6815559] [expr 3379.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[8\\\]" $west_x 3595.000 R0
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add_macro_placement "gpio_defaults_block_27" [expr $west_x + 3.6815559] [expr 3595.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[7\\\]" $west_x 3811.000 R0
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add_macro_placement "gpio_defaults_block_26" [expr $west_x + 3.6815559] [expr 3811.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[6\\\]" $west_x 4027.000 R0
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add_macro_placement "gpio_defaults_block_25" [expr $west_x + 3.6815559] [expr 4027.000 + 65] R0
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add_macro_placement "gpio_control_in_2\\\[5\\\]" $west_x 4656.000 R0
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add_macro_placement "gpio_defaults_block_24" [expr $west_x + 3.6815559] [expr 4656.000 + 65] R0
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# north
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set north_y 4980.385
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add_macro_placement "gpio_control_in_2\\\[4\\\]" 486.000 $north_y R270
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add_macro_placement "gpio_defaults_block_23" [expr 486.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_2\\\[3\\\]" 743.000 $north_y R270
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add_macro_placement "gpio_defaults_block_22" [expr 743.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_2\\\[2\\\]" 1000.000 $north_y R270
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add_macro_placement "gpio_defaults_block_21" [expr 1000.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_2\\\[1\\\]" 1257.000 $north_y R270
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add_macro_placement "gpio_defaults_block_20" [expr 1257.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_2\\\[0\\\]" 1515.000 $north_y R270
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add_macro_placement "gpio_defaults_block_19" [expr 1515.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_1\\\[10\\\]" 1767.000 $north_y R270
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add_macro_placement "gpio_defaults_block_18" [expr 1767.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_1\\\[9\\\]" 2104.000 $north_y R270
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add_macro_placement "gpio_defaults_block_17" [expr 2104.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_1\\\[8\\\]" 2489.000 $north_y R270
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add_macro_placement "gpio_defaults_block_16" [expr 2489.00 + 64.968717] [expr $north_y + 136.3215974] R270
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add_macro_placement "gpio_control_in_1\\\[7\\\]" 2746.000 $north_y R270
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add_macro_placement "gpio_defaults_block_15" [expr 2746.00 + 64.968717] [expr $north_y + 136.3215974] R270
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# east
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set east_x 3381.015
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add_macro_placement "gpio_defaults_block_0\\\[0\\\]" [expr $east_x+136.320042674] 670.000 FN
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add_macro_placement "gpio_control_bidir_1\\\[0\\\]" $east_x 605.000 MY
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add_macro_placement "gpio_defaults_block_0\\\[1\\\]" [expr $east_x+136.320042674] 896.000 FN
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add_macro_placement "gpio_control_bidir_1\\\[1\\\]" $east_x 831.000 MY
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add_macro_placement "gpio_defaults_block_2\\\[0\\\]" [expr $east_x+136.320042674] 1121.000 FN
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||||
add_macro_placement "gpio_control_in_1a\\\[0\\\]" $east_x 1056.000 MY
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add_macro_placement "gpio_defaults_block_2\\\[1\\\]" [expr $east_x+136.320042674] 1347.000 FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[1\\\]" $east_x 1282.000 MY
|
||||
add_macro_placement "gpio_defaults_block_2\\\[2\\\]" [expr $east_x+136.320042674] 1572.000 FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[2\\\]" $east_x 1507.000 MY
|
||||
add_macro_placement "gpio_defaults_block_5" [expr $east_x+136.320042674] 1797.000 FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[3\\\]" $east_x 1732.000 MY
|
||||
add_macro_placement "gpio_defaults_block_6" [expr $east_x+136.320042674] 2023.000 FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[4\\\]" $east_x 1958.000 MY
|
||||
add_macro_placement "gpio_defaults_block_7" [expr $east_x+136.320042674] 2464.000 FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[5\\\]" $east_x 2399.000 MY
|
||||
add_macro_placement "gpio_defaults_block_8" [expr $east_x+136.320042674] 2684.000 FN
|
||||
add_macro_placement "gpio_control_in_1\\\[0\\\]" $east_x 2619.000 MY
|
||||
add_macro_placement "gpio_defaults_block_9" [expr $east_x+136.320042674] 2909.000 FN
|
||||
add_macro_placement "gpio_control_in_1\\\[1\\\]" $east_x 2844.000 MY
|
||||
add_macro_placement "gpio_defaults_block_10" [expr $east_x+136.320042674] 3135.000 FN
|
||||
add_macro_placement "gpio_control_in_1\\\[2\\\]" $east_x 3070.000 MY
|
||||
add_macro_placement "gpio_defaults_block_11" [expr $east_x+136.320042674] [expr 3295.000+65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[3\\\]" $east_x 3295.000 MY
|
||||
add_macro_placement "gpio_defaults_block_12" [expr $east_x+136.320042674] [expr 3521.000+65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[4\\\]" $east_x 3521.000 MY
|
||||
add_macro_placement "gpio_defaults_block_13" [expr $east_x+136.320042674] [expr 3746.000+65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[5\\\]" $east_x 3746.000 MY
|
||||
add_macro_placement "gpio_defaults_block_14" [expr $east_x+136.320042674] [expr 4638.000+65] FN
|
||||
add_macro_placement "gpio_control_in_1\\\[6\\\]" $east_x 4638.000 MY
|
||||
add_macro_placement chip_core 211.5 210.5 N
|
||||
add_macro_placement user_id_textblock 175 35 N
|
||||
add_macro_placement copyright_block 482 85 N
|
||||
add_macro_placement open_source 768 15 N
|
||||
add_macro_placement caravel_logo 1080 25.5 N
|
||||
add_macro_placement caravel_motto 1350 -35 N
|
||||
|
||||
manual_macro_placement f
|
||||
|
||||
# modify to a different file
|
||||
remove_pins -input $::env(CURRENT_DEF)
|
||||
remove_empty_nets -input $::env(CURRENT_DEF)
|
||||
label_macro_pins \
|
||||
-lef $::env(CARAVEL_ROOT)/lef/caravel.lef \
|
||||
-netlist_def $::env(CURRENT_DEF)
|
||||
|
||||
# add routing obstruction around the user_project_wrapper to prevent
|
||||
# having shorts with the core ring or signal routing inside the wrapper
|
||||
set gap 0.4
|
||||
set user_project_wrapper_obs [list [expr $mprj_x-$gap] [expr $mprj_y-$gap] [expr $mprj_x+$gap+2920] [expr $mprj_y+$gap+3520]]
|
||||
set user_project_wrapper_core_ring_obs [list [expr $mprj_x-43.63] [expr $mprj_y-38.34] [expr $mprj_x+2963.25] [expr $mprj_y+$gap+3557.96]]
|
||||
|
||||
# add routing obstructions on the management area
|
||||
set mgmt_area_obs [list $soc_x $soc_y [expr $soc_x+2620] [expr $soc_y+820]]
|
||||
|
||||
set routing_vio_obs [list 106.26803 2098.54857 108.85254 2096.63000]
|
||||
|
||||
set ::env(GLB_RT_OBS) "
|
||||
met1 $user_project_wrapper_obs,\
|
||||
met2 $user_project_wrapper_obs,\
|
||||
met3 $user_project_wrapper_obs,\
|
||||
met4 $user_project_wrapper_core_ring_obs,\
|
||||
met4 $mgmt_area_obs,\
|
||||
met5 $user_project_wrapper_core_ring_obs,\
|
||||
met5 $mgmt_area_obs,\
|
||||
met3 $routing_vio_obs"
|
||||
|
||||
try_catch openroad -python $::env(SCRIPTS_DIR)/add_def_obstructions.py \
|
||||
--input-def $::env(CURRENT_DEF) \
|
||||
--lef $::env(MERGED_LEF) \
|
||||
--obstructions $::env(GLB_RT_OBS) \
|
||||
--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
|
||||
|
||||
set_def [file rootname $::env(CURRENT_DEF)].obs.def
|
||||
|
||||
# add_macro_obs \
|
||||
# -defFile $::env(CURRENT_DEF) \
|
||||
# -lefFile $::env(MERGED_LEF_UNPADDED) \
|
||||
# -obstruction vddio_obs \
|
||||
# -placementX 103.400 \
|
||||
# -placementY 607.150 \
|
||||
# -sizeWidth 94.500 \
|
||||
# -sizeHeight 30 \
|
||||
# -fixed 1 \
|
||||
# -layerNames "met2 met4"
|
||||
|
||||
# add_macro_obs \
|
||||
# -defFile $::env(CURRENT_DEF) \
|
||||
# -lefFile $::env(MERGED_LEF_UNPADDED) \
|
||||
# -obstruction vddio_pad_obs \
|
||||
# -placementX 33.375 \
|
||||
# -placementY 557.100 \
|
||||
# -sizeWidth 62.615 \
|
||||
# -sizeHeight 62.700 \
|
||||
# -fixed 1 \
|
||||
# -layerNames "li1 met1 met2 met3 met4 met5"
|
||||
|
||||
li1_hack_start
|
||||
save_state
|
||||
puts "WARNING: Patching the def file $::env(CURRENT_DEF) with $script_dir/power_routing_def.patch"
|
||||
puts "WARNING: this is a workaround that should be properly handled in the future"
|
||||
puts "WARNING: this is for very specific versions"
|
||||
exec patch $::env(CURRENT_DEF) < $script_dir/power_routing_def.patch
|
||||
global_routing
|
||||
detailed_routing
|
||||
li1_hack_end
|
||||
|
||||
label_macro_pins\
|
||||
-lef $::env(TMP_DIR)/lvs.lef\
|
||||
-netlist_def $::env(TMP_DIR)/lvs.def
|
||||
# -extra_args {-v\
|
||||
# --map padframe vddio vddio INOUT\
|
||||
# --map padframe vssio vssio INOUT\
|
||||
# --map padframe vssa vssa INOUT\
|
||||
# --map padframe vccd vccd INOUT\
|
||||
# --map padframe vssd vssd INOUT}
|
||||
foreach {process_corner lef ruleset} {
|
||||
min MERGED_LEF_MIN RCX_RULES_MIN
|
||||
max MERGED_LEF_MAX RCX_RULES_MAX
|
||||
nom MERGED_LEF RCX_RULES
|
||||
} {
|
||||
run_spef_extraction\
|
||||
-log $::env(signoff_logs)/parasitics_extraction.$process_corner.log\
|
||||
-rcx_lib $::env(LIB_SYNTH_COMPLETE)\
|
||||
-rcx_rules $::env($ruleset)\
|
||||
-rcx_lef $::env($lef)\
|
||||
-process_corner $process_corner \
|
||||
-save "$script_dir/$::env(DESIGN_NAME).$process_corner.spef"
|
||||
}
|
||||
|
||||
run_magic
|
||||
|
||||
run_magic_spice_export
|
||||
|
||||
save_views -lef_path $::env(magic_result_file_tag).lef \
|
||||
-def_path $::env(tritonRoute_result_file_tag).def \
|
||||
-gds_path $::env(magic_result_file_tag).gds \
|
||||
-mag_path $::env(magic_result_file_tag).mag \
|
||||
-verilog_path $::env(TMP_DIR)/lvs.v \
|
||||
-spice_path $::env(magic_result_file_tag).spice \
|
||||
-save_path $save_path \
|
||||
-tag $::env(RUN_TAG)
|
||||
|
||||
run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v
|
||||
##saves to <RUN_DIR>/results/final
|
||||
save_final_views
|
||||
save_final_views -save_path .. -tag $::env(RUN_TAG)
|
||||
##
|
||||
calc_total_runtime
|
||||
save_state
|
||||
generate_final_summary_report
|
||||
check_timing_violations
|
||||
if { [info exists arg_values(-save_path)]\
|
||||
&& $arg_values(-save_path) != "" } {
|
||||
set ::env(HOOK_OUTPUT_PATH) "[file normalize $arg_values(-save_path)]"
|
||||
} else {
|
||||
set ::env(HOOK_OUTPUT_PATH) $::env(RESULTS_DIR)/final
|
||||
}
|
||||
if {[info exists flags_map(-run_hooks)]} {
|
||||
run_post_run_hooks
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1 +1 @@
|
|||
openlane v0.22
|
||||
OpenLane 1ed36219093ce86ddbc1b981e461c5f38e5bba72
|
||||
|
|
|
|||
|
|
@ -1,6 +1 @@
|
|||
-ne openlane
|
||||
02c16938aea3770c1d2e03fc8beed763fa83f30f
|
||||
-ne skywater-pdk
|
||||
ea95157faad3a3f5c560aaec3f1841ee5a2aa2db
|
||||
-ne open_pdks
|
||||
1d93a6bd9d6e481acfdf88f26aa3bb0600303d98
|
||||
open_pdks 327e268bdb7191fe07a28bd40eeac055bba9dffd
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
|
||||
/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/caravel,caravel,23_02_27_09_47,flow completed,0h2m19s0ms,-1,-2.0,-1,-1,-1,-1,7,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,0,0,0,0,18475999.948799998,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,11.0,90.9090909090909,10.0,0,1,50,153.18,153.6,0.3,0.55,sky130_fd_sc_hd,10,AREA 0
|
||||
|
|
|
@ -285,8 +285,8 @@ module caravel (
|
|||
`ifdef USE_POWER_PINS
|
||||
.vddio(vddio_core), // Common 3.3V padframe/ESD power
|
||||
.vssio(vssio_core), // Common padframe/ESD ground
|
||||
.vdda (vdda_core), // Management 3.3V power
|
||||
.vssa (vssa_core), // Common analog ground
|
||||
// .vdda (vdda_core), // Management 3.3V power
|
||||
// .vssa (vssa_core), // Common analog ground
|
||||
.vccd (vccd_core), // Management/Common 1.8V power
|
||||
.vssd (vssd_core), // Common digital ground
|
||||
.vdda1(vdda1_core), // User area 1 3.3V power
|
||||
|
|
@ -347,5 +347,11 @@ module caravel (
|
|||
.mprj_analog_io(user_analog_io)
|
||||
);
|
||||
|
||||
copyright_block copyright_block();
|
||||
caravel_logo caravel_logo();
|
||||
caravel_motto caravel_motto();
|
||||
open_source open_source();
|
||||
user_id_textblock user_id_textblock();
|
||||
|
||||
endmodule
|
||||
// `default_nettype wire
|
||||
|
|
|
|||
Loading…
Reference in New Issue