mirror of https://github.com/efabless/caravel.git
Caravan redesign (#321)
* Fixed caravan top level power routing and updated views for mag, gds and lef
* caravan(rtl): updates
~ typos fix
- remove unused pin in chip_io_alt
+ add caravan_power_routing verilog
* Apply automatic changes to Manifest and README.rst
* ~ update caravan openlane configs to add extra cell references
~ correct placment and cell names of some macro in caravan interactive script
* reharden: caravan
+ add non functional blocks
+ add an initial iteration of caravan
* Apply automatic changes to Manifest and README.rst
* Revert "Fixed caravan top level power routing and updated views for mag, gds and lef"
This reverts commit 70628f748a.
* fixed caravan top level power routing
* reharden: caravan
based on new power routing
~ guard rtl chip_io power pins in the power macro guard
* Apply automatic changes to Manifest and README.rst
* fixed caravan top level power routing
* rehadren: caravan
+ add caravan signal routing to openlane run
~ change rtl to guard power and analog against routing by
openlane by ifndef TOP_ROUTING
~ add pr bounadry for caravan signal routing to fix origin issues
* Apply automatic changes to Manifest and README.rst
* fix power connection in buffering block and regenerate gl
* Apply automatic changes to Manifest and README.rst
* updated views for caravan
* Added extract unique to lvs-gds-cell target. (#313)
* This fixes errors in the top level RTL of caravan that failed to
hook up the buffers through the SoC correctly.
* Apply automatic changes to Manifest and README.rst
* reharden: caravan
~ rtl updated
* fixed caravan mag top level
* updated views for caravan + signoff
* fixed top level cell name
* fix syntax error related to signal initialization place in caravan (#319)
* fix syntax error related to signal initialization place in caravan- fixed in caravel in another commit
* Apply automatic changes to Manifest and README.rst
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
* Apply automatic changes to Manifest and README.rst
Co-authored-by: Marwan Abbas <marwaneltoukhy@aucegypt.edu>
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Mitch Bailey <d-m-bailey@users.noreply.github.com>
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
Co-authored-by: RTimothyEdwards <RTimothyEdwards@users.noreply.github.com>
Co-authored-by: Marwan Abbas <67271180+marwaneltoukhy@users.noreply.github.com>
Co-authored-by: M0stafaRady <107422726+M0stafaRady@users.noreply.github.com>
Co-authored-by: M0stafaRady <M0stafaRady@users.noreply.github.com>
Co-authored-by: jeffdi <jeffdi@users.noreply.github.com>
This commit is contained in:
Jeff DiCorpo
GitHub
parent
1d26e4df32
commit
4192c34f4b
1
Makefile
1
Makefile
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@ -368,6 +368,7 @@ $(LVS_GDS_BLOCKS): lvs-gds-% : ./gds/%.gds ./verilog/gl/%.v
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select top cell;\
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extract no all;\
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extract do local;\
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extract unique;\
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extract;\
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ext2spice lvs;\
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ext2spice $*.ext;\
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51749
def/caravan.def
51749
def/caravan.def
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Load Diff
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@ -0,0 +1,12 @@
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VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO caravan_logo
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CLASS BLOCK ;
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FOREIGN caravan_logo ;
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ORIGIN 0.000 0.000 ;
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SIZE 40.000 BY 25.000 ;
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END caravan_logo
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END LIBRARY
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@ -0,0 +1,12 @@
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VERSION 5.7 ;
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NOWIREEXTENSIONATPIN ON ;
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DIVIDERCHAR "/" ;
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BUSBITCHARS "[]" ;
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MACRO caravan_motto
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CLASS BLOCK ;
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END LIBRARY
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,265 @@
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VERSION 5.7 ;
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MACRO caravan_signal_routing
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|
||||
RECT 1879.000 4969.100 1946.395 4978.100 ;
|
||||
RECT 1976.390 4969.100 2043.785 4978.100 ;
|
||||
LAYER met5 ;
|
||||
RECT 1105.000 4967.100 1176.395 4980.100 ;
|
||||
POLYGON 1105.000 4967.100 1154.510 4967.100 1154.510 4917.590 ;
|
||||
RECT 1154.510 4917.590 1176.395 4967.100 ;
|
||||
RECT 1202.390 4969.100 1273.785 4980.100 ;
|
||||
RECT 1202.390 4960.580 1274.000 4969.100 ;
|
||||
RECT 1202.390 4921.210 1231.010 4960.580 ;
|
||||
POLYGON 1202.390 4921.210 1206.010 4921.210 1206.010 4917.590 ;
|
||||
RECT 1154.510 4913.590 1179.510 4917.590 ;
|
||||
RECT 1206.010 4913.590 1231.010 4921.210 ;
|
||||
POLYGON 1231.010 4960.580 1274.000 4960.580 1231.010 4917.590 ;
|
||||
RECT 1368.000 4962.600 1439.395 4980.100 ;
|
||||
POLYGON 1368.000 4962.600 1413.010 4962.600 1413.010 4917.590 ;
|
||||
RECT 1413.010 4918.975 1439.395 4962.600 ;
|
||||
RECT 1413.010 4913.590 1438.010 4918.975 ;
|
||||
POLYGON 1438.010 4918.975 1439.395 4918.975 1438.010 4917.590 ;
|
||||
RECT 1465.390 4969.100 1536.785 4980.100 ;
|
||||
RECT 1465.390 4965.080 1537.000 4969.100 ;
|
||||
RECT 1465.390 4917.590 1489.510 4965.080 ;
|
||||
POLYGON 1489.510 4965.080 1537.000 4965.080 1489.510 4917.590 ;
|
||||
RECT 1877.000 4962.100 1948.395 4980.100 ;
|
||||
POLYGON 1877.000 4962.100 1921.510 4962.100 1921.510 4917.590 ;
|
||||
RECT 1921.510 4919.475 1948.395 4962.100 ;
|
||||
RECT 1464.510 4913.590 1489.510 4917.590 ;
|
||||
RECT 1921.510 4913.590 1946.510 4919.475 ;
|
||||
POLYGON 1946.510 4919.475 1948.395 4919.475 1946.510 4917.590 ;
|
||||
RECT 1974.390 4969.100 2045.785 4980.100 ;
|
||||
RECT 1974.390 4965.580 2046.000 4969.100 ;
|
||||
RECT 1974.390 4917.590 1998.010 4965.580 ;
|
||||
POLYGON 1998.010 4965.580 2046.000 4965.580 1998.010 4917.590 ;
|
||||
RECT 1973.010 4913.590 1998.010 4917.590 ;
|
||||
END
|
||||
END caravan_signal_routing
|
||||
END LIBRARY
|
||||
|
||||
|
|
@ -0,0 +1,12 @@
|
|||
VERSION 5.7 ;
|
||||
NOWIREEXTENSIONATPIN ON ;
|
||||
DIVIDERCHAR "/" ;
|
||||
BUSBITCHARS "[]" ;
|
||||
MACRO copyright_block_a
|
||||
CLASS BLOCK ;
|
||||
FOREIGN copyright_block_a ;
|
||||
ORIGIN 0.000 0.000 ;
|
||||
SIZE 40.000 BY 25.000 ;
|
||||
END copyright_block_a
|
||||
END LIBRARY
|
||||
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
131112
mag/caravan.mag
131112
mag/caravan.mag
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -1,7 +1,7 @@
|
|||
magic
|
||||
tech sky130A
|
||||
magscale 1 2
|
||||
timestamp 1649950523
|
||||
timestamp 1666277172
|
||||
<< checkpaint >>
|
||||
rect 39764 415548 677806 997846
|
||||
<< metal3 >>
|
||||
|
|
@ -303,4 +303,6 @@ rect 394878 993116 409200 993820
|
|||
rect 394878 983518 399602 993116
|
||||
tri 399602 983518 409200 993116 nw
|
||||
rect 394602 982718 399602 983518
|
||||
<< properties >>
|
||||
string FIXED_BBOX 0 0 717600 1037600
|
||||
<< end >>
|
||||
|
|
|
|||
5
manifest
5
manifest
|
|
@ -5,9 +5,10 @@
|
|||
5f8e2d6670ce912bc209201d23430f62730e2627 verilog/rtl/__user_project_la_example.v
|
||||
cc82a78753f5f5d0a1519bd81adbcff8a4296d91 verilog/rtl/__user_project_wrapper.v
|
||||
3c8c04f53b2848dc46132cda82c614e06e56571b verilog/rtl/buff_flash_clkrst.v
|
||||
2cc670e819a1cae69314242364118f5d4267737c verilog/rtl/caravan.v
|
||||
2a5a008b29a1f494010e9245d56dbefd770e61f0 verilog/rtl/caravan.v
|
||||
06e92151b5928e3f28e30a5cde76f7dd6530ed91 verilog/rtl/caravan_netlists.v
|
||||
a3d12a2d2d3596800bec47d1266dce2399a2fcc6 verilog/rtl/caravan_openframe.v
|
||||
b532b4c6315c29fd19fe38ac221b6fc41e6f5ecb verilog/rtl/caravan_power_routing.v
|
||||
b38b8911910265a96d8248095964a5ee8139820b verilog/rtl/caravel.v
|
||||
2fe34f043edbe87c626e5616ad54f82c9ba067c2 verilog/rtl/caravel_clocking.v
|
||||
625c9f974f1a3c9bd2eca5449a89a7bfb8f69fe8 verilog/rtl/caravel_logo.v
|
||||
|
|
@ -15,7 +16,7 @@ b38b8911910265a96d8248095964a5ee8139820b verilog/rtl/caravel.v
|
|||
3b9185fd0dc2d0e8c49f1af3d14724e0948fe650 verilog/rtl/caravel_openframe.v
|
||||
d97cb60c8d125d6098111d4f0aa00410515770eb verilog/rtl/caravel_power_routing.v
|
||||
bc1e961e41d1d3a383a018279a08bf4108911f53 verilog/rtl/chip_io.v
|
||||
97c958944dd74a87f75d9fe2309837e567468722 verilog/rtl/chip_io_alt.v
|
||||
f2242e1f295ee5efeacea51698f706a2cfd97c28 verilog/rtl/chip_io_alt.v
|
||||
126aff02aa229dc346301c552d785dec76a4d68e verilog/rtl/clock_div.v
|
||||
941bd7636e7558b045faa3d8c6ba2d91b4c4b798 verilog/rtl/constant_block.v
|
||||
58fd210a64e502fb231d843eada4052f923d788d verilog/rtl/copyright_block.v
|
||||
|
|
|
|||
|
|
@ -20,9 +20,9 @@ set ::env(DESIGN_NAME) caravan
|
|||
|
||||
set ::env(STD_CELL_LIBRARY_OPT) "sky130_fd_sc_hd"
|
||||
|
||||
set verilog_root $script_dir/../../verilog/
|
||||
set lef_root $script_dir/../../lef/
|
||||
set gds_root $script_dir/../../gds/
|
||||
set verilog_root $::env(CARAVEL_ROOT)/verilog/
|
||||
set lef_root $::env(CARAVEL_ROOT)/lef/
|
||||
set gds_root $::env(CARAVEL_ROOT)/gds/
|
||||
|
||||
set mgmt_area_verilog_root $::env(MCW_ROOT)/verilog/
|
||||
set mgmt_area_lef_root $::env(MCW_ROOT)/lef/
|
||||
|
|
@ -30,60 +30,87 @@ set mgmt_area_gds_root $::env(MCW_ROOT)/gds/
|
|||
|
||||
# Change if needed
|
||||
set ::env(VERILOG_FILES) "\
|
||||
$verilog_root/rtl/user_defines.v \
|
||||
$verilog_root/rtl/user_defines.v
|
||||
$verilog_root/rtl/caravan.v"
|
||||
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) 1
|
||||
|
||||
|
||||
# defines and pads need to be first
|
||||
# order matters
|
||||
set ::env(VERILOG_FILES_BLACKBOX) "\
|
||||
$verilog_root/rtl/defines.v \
|
||||
$verilog_root/rtl/defines.v
|
||||
$verilog_root/rtl/pads.v \
|
||||
$verilog_root/rtl/chip_io_alt.v \
|
||||
$mgmt_area_verilog_root/rtl/mgmt_core_wrapper.v \
|
||||
$verilog_root/rtl/__user_analog_project_wrapper.v \
|
||||
$verilog_root/rtl/mgmt_protect.v \
|
||||
$verilog_root/rtl/gpio_defaults_block.v \
|
||||
$verilog_root/rtl/gpio_control_block.v \
|
||||
$verilog_root/rtl/user_id_programming.v \
|
||||
$verilog_root/rtl/housekeeping.v \
|
||||
$verilog_root/rtl/digital_pll.v \
|
||||
$verilog_root/rtl/buff_flash_clkrst.v \
|
||||
$verilog_root/rtl/caravan_power_routing.v \
|
||||
$verilog_root/rtl/caravel_clocking.v \
|
||||
$verilog_root/rtl/caravan_signal_routing.v \
|
||||
$verilog_root/rtl/chip_io_alt.v \
|
||||
$verilog_root/rtl/digital_pll.v \
|
||||
$verilog_root/rtl/gpio_control_block.v \
|
||||
$verilog_root/rtl/gpio_defaults_block.v \
|
||||
$verilog_root/rtl/gpio_signal_buffering_alt.v \
|
||||
$verilog_root/rtl/housekeeping.v \
|
||||
$verilog_root/rtl/mgmt_protect.v \
|
||||
$verilog_root/rtl/simple_por.v\
|
||||
$verilog_root/rtl/spare_logic_block.v\
|
||||
$verilog_root/rtl/user_id_programming.v \
|
||||
$verilog_root/rtl/xres_buf.v \
|
||||
$verilog_root/rtl/caravan_power_routing.v \
|
||||
$mgmt_area_verilog_root/rtl/mgmt_core_wrapper.v \
|
||||
$verilog_root/rtl/caravan_logo.v \
|
||||
$verilog_root/rtl/caravan_motto.v \
|
||||
$verilog_root/rtl/copyright_block_a.v \
|
||||
$verilog_root/rtl/open_source.v \
|
||||
$verilog_root/rtl/user_id_textblock.v \
|
||||
"
|
||||
|
||||
set ::env(EXTRA_LEFS) "\
|
||||
$lef_root/caravan_signal_routing.lef \
|
||||
$lef_root/caravan_logo-stub.lef \
|
||||
$lef_root/caravan_motto-stub.lef \
|
||||
$lef_root/copyright_block_a-stub.lef \
|
||||
$lef_root/open_source-stub.lef \
|
||||
$lef_root/user_id_textblock-stub.lef \
|
||||
$lef_root/buff_flash_clkrst.lef\
|
||||
$lef_root/caravan_power_routing.lef\
|
||||
$lef_root/caravel_clocking.lef \
|
||||
$lef_root/chip_io_alt.lef \
|
||||
$lef_root/user_analog_project_wrapper.lef \
|
||||
$lef_root/mgmt_protect.lef \
|
||||
$lef_root/digital_pll.lef \
|
||||
$lef_root/gpio_control_block.lef \
|
||||
$lef_root/gpio_defaults_block.lef \
|
||||
$lef_root/user_id_programming.lef \
|
||||
$lef_root/gpio_signal_buffering_alt.lef\
|
||||
$lef_root/housekeeping.lef \
|
||||
$lef_root/digital_pll.lef \
|
||||
$lef_root/caravel_clocking.lef \
|
||||
$lef_root/mgmt_protect.lef \
|
||||
$lef_root/simple_por.lef\
|
||||
$lef_root/xres_buf.lef\
|
||||
$lef_root/caravan_power_routing.lef\
|
||||
$lef_root/spare_logic_block.lef\
|
||||
$lef_root/user_analog_project_wrapper.lef \
|
||||
$lef_root/user_id_programming.lef \
|
||||
$lef_root/xres_buf.lef\
|
||||
$mgmt_area_lef_root/mgmt_core_wrapper.lef \
|
||||
"
|
||||
|
||||
set ::env(EXTRA_GDS_FILES) "\
|
||||
$gds_root/caravan_signal_routing.gds \
|
||||
$gds_root/caravan_logo.gds \
|
||||
$gds_root/caravan_motto.gds \
|
||||
$gds_root/copyright_block_a.gds \
|
||||
$gds_root/open_source.gds \
|
||||
$gds_root/user_id_textblock.gds \
|
||||
$gds_root/caravel_clocking.gds \
|
||||
$gds_root/chip_io_alt.gds \
|
||||
$gds_root/user_analog_project_wrapper.gds \
|
||||
$gds_root/mgmt_protect.gds \
|
||||
$gds_root/digital_pll.gds \
|
||||
$gds_root/gpio_control_block.gds \
|
||||
$gds_root/gpio_defaults_block.gds \
|
||||
$gds_root/user_id_programming.gds \
|
||||
$gds_root/housekeeping.gds \
|
||||
$gds_root/digital_pll.gds \
|
||||
$gds_root/caravel_clocking.gds \
|
||||
$gds_root/mgmt_protect.gds \
|
||||
$gds_root/simple_por.gds\
|
||||
$gds_root/user_analog_project_wrapper.gds \
|
||||
$gds_root/user_id_programming.gds \
|
||||
$gds_root/xres_buf.gds\
|
||||
$mgmt_area_gds_root/mgmt_core_wrapper.gds \
|
||||
$gds_root/buff_flash_clkrst.gds \
|
||||
$gds_root/gpio_signal_buffering_alt.gds \
|
||||
"
|
||||
|
||||
# # !!!
|
||||
|
|
@ -119,12 +146,14 @@ set ::env(GLB_RT_MAXLAYER) 6
|
|||
|
||||
set ::env(GLB_RT_ADJUSTMENT) "0"
|
||||
set ::env(GLB_RT_L1_ADJUSTMENT) "0.99"
|
||||
set ::env(GLB_RT_L2_ADJUSTMENT) "0.1"
|
||||
set ::env(GLB_RT_L3_ADJUSTMENT) "0.15"
|
||||
set ::env(GLB_RT_L4_ADJUSTMENT) "0.15"
|
||||
set ::env(GLB_RT_L5_ADJUSTMENT) "0.15"
|
||||
set ::env(GLB_RT_L2_ADJUSTMENT) "0.15"
|
||||
set ::env(GLB_RT_L3_ADJUSTMENT) "0.45"
|
||||
set ::env(GLB_RT_L4_ADJUSTMENT) "0.45"
|
||||
set ::env(GLB_RT_L5_ADJUSTMENT) "0.45"
|
||||
set ::env(GLB_RT_L6_ADJUSTMENT) "0"
|
||||
|
||||
set ::env(TECH_LEF) $::env(DESIGN_DIR)/sky130_fd_sc_hd.tlef
|
||||
|
||||
# set ::env(ROUTING_OPT_ITERS) 7
|
||||
# set ::env(GLB_RT_UNIDIRECTIONAL) 0
|
||||
|
||||
|
|
|
|||
|
|
@ -50,24 +50,32 @@ set mprj_y 1393.590
|
|||
set soc_x 260.170
|
||||
set soc_y 265.010
|
||||
|
||||
add_macro_placement fake_caravan_power_routing 0 0 N
|
||||
add_macro_placement caravan_power_routing 0 0 N
|
||||
add_macro_placement caravan_signal_routing 0 0 N
|
||||
add_macro_placement user_id_textblock 481.36000 34.45000 N
|
||||
add_macro_placement copyright_block_a 747.91000 81.49000 N
|
||||
add_macro_placement open_source 1030.37000 11.68000 N
|
||||
add_macro_placement caravan_logo 1276.50000 30.16000 N
|
||||
add_macro_placement caravan_motto -272.80000 -0.26000 N
|
||||
add_macro_placement sigbuf 0 0 N
|
||||
add_macro_placement flash_clkrst_buffers 2292 238 N
|
||||
add_macro_placement padframe 0 0 N
|
||||
add_macro_placement soc $soc_x $soc_y N
|
||||
add_macro_placement housekeeping 3032.170 500.010 N
|
||||
add_macro_placement housekeeping 2962.17 500.010 N
|
||||
add_macro_placement mprj $mprj_x $mprj_y N
|
||||
add_macro_placement mgmt_buffers 960.900 1160.180 N
|
||||
add_macro_placement mgmt_buffers 640.900 1160.180 N
|
||||
# add_macro_placement mgmt_buffers 1060.850 1234.090 N
|
||||
add_macro_placement rstb_level 708.550 235.440 S
|
||||
add_macro_placement user_id_value 3283.120 440.630 N
|
||||
add_macro_placement por 3250.730 234.721 MX
|
||||
add_macro_placement pll 3140.730 404.721 N
|
||||
|
||||
add_macro_placement clock_ctrl 3108.42000 318.04000 N
|
||||
add_macro_placement clock_ctrl 3133.820 276.420 N
|
||||
|
||||
add_macro_placement spare_logic\\\[0\\\] 443.16 1162.64 N
|
||||
add_macro_placement spare_logic\\\[1\\\] 843.16 1162.64 N
|
||||
add_macro_placement spare_logic\\\[1\\\] 543.16 1162.64 N
|
||||
add_macro_placement spare_logic\\\[2\\\] 3204.37 1102.96 N
|
||||
add_macro_placement spare_logic\\\[3\\\] 2143.16 1162.64 N
|
||||
add_macro_placement spare_logic\\\[3\\\] 2893.16 1162.64 N
|
||||
|
||||
|
||||
# west
|
||||
|
|
@ -108,25 +116,25 @@ add_macro_placement "gpio_control_in_2\\\[2\\\]" $west_x 3595.000 R0
|
|||
add_macro_placement "gpio_defaults_block_26" [expr $west_x + 3.6815559] [expr 3811.000 + 65] R0
|
||||
add_macro_placement "gpio_control_in_2\\\[1\\\]" $west_x 3811.000 R0
|
||||
|
||||
add_macro_placement "gpio_defaults_block_14" [expr $west_x + 3.6815559] [expr 4027.000 + 65] R0
|
||||
add_macro_placement "gpio_defaults_block_25" [expr $west_x + 3.6815559] [expr 4027.000 + 65] R0
|
||||
add_macro_placement "gpio_control_in_2\\\[0\\\]" $west_x 4027.000 R0
|
||||
|
||||
# east
|
||||
set east_x 3381.015
|
||||
|
||||
add_macro_placement "gpio_defaults_block_0\\\[0\\\]" [expr $east_x+136.320042674] [expr 605 + 65] FN
|
||||
add_macro_placement "gpio_defaults_block_0" [expr $east_x+136.320042674] [expr 605 + 65] FN
|
||||
add_macro_placement "gpio_control_bidir_1\\\[0\\\]" $east_x 605.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_0\\\[1\\\]" [expr $east_x+136.320042674] [expr 831 + 65] FN
|
||||
add_macro_placement "gpio_defaults_block_1" [expr $east_x+136.320042674] [expr 831 + 65] FN
|
||||
add_macro_placement "gpio_control_bidir_1\\\[1\\\]" $east_x 831.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_2\\\[0\\\]" [expr $east_x+136.320042674] [expr 1056 + 65] FN
|
||||
add_macro_placement "gpio_defaults_block_2" [expr $east_x+136.320042674] [expr 1056 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[0\\\]" $east_x 1056.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_2\\\[1\\\]" [expr $east_x+136.320042674] [expr 1282 + 65] FN
|
||||
add_macro_placement "gpio_defaults_block_3" [expr $east_x+136.320042674] [expr 1282 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[1\\\]" $east_x 1282.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_2\\\[2\\\]" [expr $east_x+136.320042674] [expr 1507 + 65] FN
|
||||
add_macro_placement "gpio_defaults_block_4" [expr $east_x+136.320042674] [expr 1507 + 65] FN
|
||||
add_macro_placement "gpio_control_in_1a\\\[2\\\]" $east_x 1507.000 MY
|
||||
|
||||
add_macro_placement "gpio_defaults_block_5" [expr $east_x+136.320042674] [expr 1732 + 65] FN
|
||||
|
|
@ -194,19 +202,18 @@ set ::env(GLB_RT_OBS) "\
|
|||
met5 $mgmt_area_obs,\
|
||||
$wrapper_obs"
|
||||
|
||||
try_catch python3 $::env(SCRIPTS_DIR)/add_def_obstructions.py \
|
||||
try_catch openroad -python $::env(SCRIPTS_DIR)/add_def_obstructions.py \
|
||||
--input-def $::env(CURRENT_DEF) \
|
||||
--lef $::env(MERGED_LEF) \
|
||||
--obstructions $::env(GLB_RT_OBS) \
|
||||
--output [file rootname $::env(CURRENT_DEF)].obs.def |& tee $::env(TERMINAL_OUTPUT) $::env(LOG_DIR)/obs.log
|
||||
|
||||
set_def [file rootname $::env(CURRENT_DEF)].obs.def
|
||||
|
||||
li1_hack_start
|
||||
global_routing
|
||||
detailed_routing
|
||||
li1_hack_end
|
||||
exec sed -i "/.*fake_caravan_power_routing.*/d" $::env(CURRENT_DEF)
|
||||
puts "\[INTERATCIVE\] removed fake_caravan_power_routing from $::env(CURRENT_DEF)"
|
||||
|
||||
label_macro_pins\
|
||||
-lef $::env(TMP_DIR)/lvs.lef\
|
||||
|
|
@ -220,15 +227,13 @@ label_macro_pins\
|
|||
|
||||
run_magic
|
||||
|
||||
run_magic_spice_export
|
||||
save_views\
|
||||
-def_path $::env(CURRENT_DEF) \
|
||||
-gds_path $::env(magic_result_file_tag).gds \
|
||||
-mag_path $::env(magic_result_file_tag).mag \
|
||||
-verilog_path $::env(TMP_DIR)/lvs.v \
|
||||
-save_path $save_path \
|
||||
-tag caravan
|
||||
|
||||
save_views -lef_path $::env(magic_result_file_tag).lef \
|
||||
-def_path $::env(tritonRoute_result_file_tag).def \
|
||||
-gds_path $::env(magic_result_file_tag).gds \
|
||||
-mag_path $::env(magic_result_file_tag).mag \
|
||||
-verilog_path $::env(TMP_DIR)/lvs.v \
|
||||
-spice_path $::env(magic_result_file_tag).spice \
|
||||
-save_path $save_path \
|
||||
-tag $::env(RUN_TAG)
|
||||
exit
|
||||
|
||||
run_lvs $::env(magic_result_file_tag).spice $::env(TMP_DIR)/lvs.v
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -61,24 +61,26 @@
|
|||
/*--------------------------------------------------------------*/
|
||||
|
||||
module caravan (
|
||||
inout vddio, // Common 3.3V padframe/ESD power
|
||||
inout vddio_2, // Common 3.3V padframe/ESD power
|
||||
inout vssio, // Common padframe/ESD ground
|
||||
inout vssio_2, // Common padframe/ESD ground
|
||||
inout vdda, // Management 3.3V power
|
||||
inout vssa, // Common analog ground
|
||||
inout vccd, // Management/Common 1.8V power
|
||||
inout vssd, // Common digital ground
|
||||
inout vdda1, // User area 1 3.3V power
|
||||
inout vdda1_2, // User area 1 3.3V power
|
||||
inout vdda2, // User area 2 3.3V power
|
||||
inout vssa1, // User area 1 analog ground
|
||||
inout vssa1_2, // User area 1 analog ground
|
||||
inout vssa2, // User area 2 analog ground
|
||||
inout vccd1, // User area 1 1.8V power
|
||||
inout vccd2, // User area 2 1.8V power
|
||||
inout vssd1, // User area 1 digital ground
|
||||
inout vssd2, // User area 2 digital ground
|
||||
`ifndef TOP_ROUTING
|
||||
inout vddio, // Common 3.3V padframe/ESD power
|
||||
inout vddio_2, // Common 3.3V padframe/ESD power
|
||||
inout vssio, // Common padframe/ESD ground
|
||||
inout vssio_2, // Common padframe/ESD ground
|
||||
inout vdda, // Management 3.3V power
|
||||
inout vssa, // Common analog ground
|
||||
inout vccd, // Management/Common 1.8V power
|
||||
inout vssd, // Common digital ground
|
||||
inout vdda1, // User area 1 3.3V power
|
||||
inout vdda1_2, // User area 1 3.3V power
|
||||
inout vdda2, // User area 2 3.3V power
|
||||
inout vssa1, // User area 1 analog ground
|
||||
inout vssa1_2, // User area 1 analog ground
|
||||
inout vssa2, // User area 2 analog ground
|
||||
inout vccd1, // User area 1 1.8V power
|
||||
inout vccd2, // User area 2 1.8V power
|
||||
inout vssd1, // User area 1 digital ground
|
||||
inout vssd2, // User area 2 digital ground
|
||||
`endif
|
||||
|
||||
inout gpio, // Used for external LDO control
|
||||
inout [`MPRJ_IO_PADS-1:0] mprj_io,
|
||||
|
|
@ -237,7 +239,6 @@ module caravan (
|
|||
// Flash SPI communication (managment SoC to housekeeping)
|
||||
wire flash_clk_core, flash_csb_core;
|
||||
wire flash_clk_oeb_core, flash_csb_oeb_core;
|
||||
wire flash_clk_ieb_core, flash_csb_ieb_core;
|
||||
wire flash_io0_oeb_core, flash_io1_oeb_core;
|
||||
wire flash_io2_oeb_core, flash_io3_oeb_core;
|
||||
wire flash_io0_ieb_core, flash_io1_ieb_core;
|
||||
|
|
@ -251,13 +252,81 @@ module caravan (
|
|||
wire flash_clk_frame;
|
||||
wire flash_csb_frame;
|
||||
wire flash_clk_oeb, flash_csb_oeb;
|
||||
wire flash_clk_ieb, flash_csb_ieb;
|
||||
wire flash_io0_oeb, flash_io1_oeb;
|
||||
wire flash_io0_ieb, flash_io1_ieb;
|
||||
wire flash_io0_do, flash_io1_do;
|
||||
wire flash_io0_di, flash_io1_di;
|
||||
|
||||
`ifndef NO_TOP_LEVEL_BUFFERING
|
||||
// Flash buffered signals
|
||||
wire flash_clk_frame_buf;
|
||||
wire flash_csb_frame_buf;
|
||||
wire flash_io0_oeb_buf, flash_io1_oeb_buf;
|
||||
wire flash_io0_ieb_buf, flash_io1_ieb_buf;
|
||||
wire flash_io0_do_buf, flash_io1_do_buf;
|
||||
wire flash_io0_di_buf, flash_io1_di_buf;
|
||||
|
||||
// Clock and reset buffered signals
|
||||
wire caravel_clk_buf;
|
||||
wire caravel_rstn_buf;
|
||||
wire clock_core_buf;
|
||||
|
||||
// SoC pass through buffered signals
|
||||
wire mprj_io_loader_clock_buf;
|
||||
wire mprj_io_loader_strobe_buf;
|
||||
wire mprj_io_loader_resetn_buf;
|
||||
wire mprj_io_loader_data_2_buf;
|
||||
wire rstb_l_buf;
|
||||
wire por_l_buf;
|
||||
wire porb_h_buf;
|
||||
|
||||
// SoC core
|
||||
wire caravel_clk;
|
||||
wire caravel_clk2;
|
||||
wire caravel_rstn;
|
||||
|
||||
// top-level buffers
|
||||
buff_flash_clkrst flash_clkrst_buffers (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd_core),
|
||||
.VGND(vssd_core),
|
||||
`endif
|
||||
.in_n({
|
||||
caravel_clk,
|
||||
caravel_rstn,
|
||||
flash_clk_frame,
|
||||
flash_csb_frame,
|
||||
flash_clk_oeb,
|
||||
flash_csb_oeb,
|
||||
flash_io0_oeb,
|
||||
flash_io1_oeb,
|
||||
flash_io0_ieb,
|
||||
flash_io1_ieb,
|
||||
flash_io0_do,
|
||||
flash_io1_do }),
|
||||
.in_s({
|
||||
clock_core,
|
||||
flash_io1_di,
|
||||
flash_io0_di }),
|
||||
.out_s({
|
||||
caravel_clk_buf,
|
||||
caravel_rstn_buf,
|
||||
flash_clk_frame_buf,
|
||||
flash_csb_frame_buf,
|
||||
flash_clk_oeb_buf,
|
||||
flash_csb_oeb_buf,
|
||||
flash_io0_oeb_buf,
|
||||
flash_io1_oeb_buf,
|
||||
flash_io0_ieb_buf,
|
||||
flash_io1_ieb_buf,
|
||||
flash_io0_do_buf,
|
||||
flash_io1_do_buf }),
|
||||
.out_n({
|
||||
clock_core_buf,
|
||||
flash_io1_di_buf,
|
||||
flash_io0_di_buf })
|
||||
);
|
||||
|
||||
`ifdef NO_TOP_LEVEL_BUFFERING
|
||||
assign mgmt_io_in_hk = mgmt_io_in;
|
||||
assign mgmt_io_out = mgmt_io_out_hk;
|
||||
assign mgmt_io_oeb = mgmt_io_oeb_hk;
|
||||
|
|
@ -267,16 +336,16 @@ module caravan (
|
|||
assign mgmt_io_out[6:0] = mgmt_io_out_hk[6:0];
|
||||
assign mgmt_io_oeb[34:0] = mgmt_io_oeb_hk[34:0];
|
||||
|
||||
/* The following are no-connects in caravan (no associated GPIO)
|
||||
/* The following are no-connects in caravan (no associated GPIO) */
|
||||
assign mgmt_io_in_hk[24:14] = mgmt_io_in[24:14];
|
||||
assign mgmt_io_out[24:14] = mgmt_io_out_hk[24:14];
|
||||
|
||||
gpio_signal_buffering_alt sigbuf (
|
||||
`ifdef USE_POWER_PINS
|
||||
.vccd(vccd),
|
||||
.vssd(vssd),
|
||||
.vccd(vccd_core),
|
||||
.vssd(vssd_core),
|
||||
`endif
|
||||
.mgmt_io_in_unbuf(mgmt_io_in[37:7]),
|
||||
.mgmt_io_in_unbuf({mgmt_io_in[37:25],mgmt_io_in[13:7]}),
|
||||
.mgmt_io_out_unbuf({mgmt_io_out_hk[37:25],mgmt_io_out_hk[13:7]}),
|
||||
.mgmt_io_oeb_unbuf(mgmt_io_oeb_hk[37:35]),
|
||||
.mgmt_io_in_buf({mgmt_io_in_hk[37:25],mgmt_io_in_hk[13:7]}),
|
||||
|
|
@ -309,23 +378,23 @@ module caravan (
|
|||
.vccd2_pad (vccd2), // User area 2 1.8V supply
|
||||
.vssd1_pad (vssd1), // User area 1 digital ground
|
||||
.vssd2_pad (vssd2), // User area 2 digital ground
|
||||
.vddio (vddio_core),
|
||||
.vssio (vssio_core),
|
||||
.vdda (vdda_core),
|
||||
.vssa (vssa_core),
|
||||
.vccd (vccd_core),
|
||||
.vssd (vssd_core),
|
||||
.vdda1 (vdda1_core),
|
||||
.vdda2 (vdda2_core),
|
||||
.vssa1 (vssa1_core),
|
||||
.vssa2 (vssa2_core),
|
||||
.vccd1 (vccd1_core),
|
||||
.vccd2 (vccd2_core),
|
||||
.vssd1 (vssd1_core),
|
||||
.vssd2 (vssd2_core),
|
||||
`endif
|
||||
|
||||
// Core Side Pins
|
||||
.vddio (vddio_core),
|
||||
.vssio (vssio_core),
|
||||
.vdda (vdda_core),
|
||||
.vssa (vssa_core),
|
||||
.vccd (vccd_core),
|
||||
.vssd (vssd_core),
|
||||
.vdda1 (vdda1_core),
|
||||
.vdda2 (vdda2_core),
|
||||
.vssa1 (vssa1_core),
|
||||
.vssa2 (vssa2_core),
|
||||
.vccd1 (vccd1_core),
|
||||
.vccd2 (vccd2_core),
|
||||
.vssd1 (vssd1_core),
|
||||
.vssd2 (vssd2_core),
|
||||
.gpio(gpio),
|
||||
.mprj_io(mprj_io),
|
||||
.clock(clock),
|
||||
|
|
@ -336,7 +405,7 @@ module caravan (
|
|||
.flash_io1(flash_io1),
|
||||
// SoC Core Interface
|
||||
.porb_h(porb_h),
|
||||
.por(por_l),
|
||||
.por(por_l_buf),
|
||||
.resetb_core_h(rstb_h),
|
||||
.clock_core(clock_core),
|
||||
.gpio_out_core(gpio_out_core),
|
||||
|
|
@ -345,18 +414,16 @@ module caravan (
|
|||
.gpio_mode1_core(gpio_mode1_core),
|
||||
.gpio_outenb_core(gpio_outenb_core),
|
||||
.gpio_inenb_core(gpio_inenb_core),
|
||||
.flash_csb_core(flash_csb_frame),
|
||||
.flash_clk_core(flash_clk_frame),
|
||||
.flash_csb_oeb_core(flash_csb_oeb),
|
||||
.flash_clk_oeb_core(flash_clk_oeb),
|
||||
.flash_io0_oeb_core(flash_io0_oeb),
|
||||
.flash_io1_oeb_core(flash_io1_oeb),
|
||||
.flash_csb_ieb_core(flash_csb_ieb),
|
||||
.flash_clk_ieb_core(flash_clk_ieb),
|
||||
.flash_io0_ieb_core(flash_io0_ieb),
|
||||
.flash_io1_ieb_core(flash_io1_ieb),
|
||||
.flash_io0_do_core(flash_io0_do),
|
||||
.flash_io1_do_core(flash_io1_do),
|
||||
.flash_csb_core(flash_csb_frame_buf),
|
||||
.flash_clk_core(flash_clk_frame_buf),
|
||||
.flash_csb_oeb_core(flash_csb_oeb_buf),
|
||||
.flash_clk_oeb_core(flash_clk_oeb_buf),
|
||||
.flash_io0_oeb_core(flash_io0_oeb_buf),
|
||||
.flash_io1_oeb_core(flash_io1_oeb_buf),
|
||||
.flash_io0_ieb_core(flash_io0_ieb_buf),
|
||||
.flash_io1_ieb_core(flash_io1_ieb_buf),
|
||||
.flash_io0_do_core(flash_io0_do_buf),
|
||||
.flash_io1_do_core(flash_io1_do_buf),
|
||||
.flash_io0_di_core(flash_io0_di),
|
||||
.flash_io1_di_core(flash_io1_di),
|
||||
.mprj_io_one(mprj_io_one),
|
||||
|
|
@ -380,10 +447,7 @@ module caravan (
|
|||
.mprj_clamp_low(user_clamp_low)
|
||||
);
|
||||
|
||||
// SoC core
|
||||
wire caravel_clk;
|
||||
wire caravel_clk2;
|
||||
wire caravel_rstn;
|
||||
|
||||
|
||||
wire [7:0] spi_ro_config_core;
|
||||
|
||||
|
|
@ -424,8 +488,8 @@ module caravan (
|
|||
wire [3:0] mprj_sel_o_user;
|
||||
wire [31:0] mprj_adr_o_user;
|
||||
wire [31:0] mprj_dat_o_user;
|
||||
wire mprj_ack_i_user;
|
||||
wire [31:0] mprj_dat_i_user;
|
||||
wire mprj_ack_i_user;
|
||||
|
||||
// Mask revision
|
||||
wire [31:0] mask_rev;
|
||||
|
|
@ -455,19 +519,38 @@ module caravan (
|
|||
wire clk_passthru;
|
||||
wire resetn_passthru;
|
||||
|
||||
// NC passthru signal porb_h
|
||||
wire porb_h_out_nc;
|
||||
|
||||
mgmt_core_wrapper soc (
|
||||
`ifdef USE_POWER_PINS
|
||||
.VPWR(vccd_core),
|
||||
.VGND(vssd_core),
|
||||
`endif
|
||||
|
||||
// Clocks and reset
|
||||
.core_clk(caravel_clk),
|
||||
.core_rstn(caravel_rstn),
|
||||
// SoC pass through buffered signals
|
||||
.serial_clock_in(mprj_io_loader_clock),
|
||||
.serial_clock_out(mprj_io_loader_clock_buf),
|
||||
.serial_load_in(mprj_io_loader_strobe),
|
||||
.serial_load_out(mprj_io_loader_strobe_buf),
|
||||
.serial_resetn_in(mprj_io_loader_resetn),
|
||||
.serial_resetn_out(mprj_io_loader_resetn_buf),
|
||||
.serial_data_2_in(mprj_io_loader_data_2),
|
||||
.serial_data_2_out(mprj_io_loader_data_2_buf),
|
||||
.rstb_l_in(rstb_l),
|
||||
.rstb_l_out(rstb_l_buf),
|
||||
.porb_h_in(por_l), // NOTE: purposefully tied off to por_l_in
|
||||
.porb_h_out(porb_h_out_nc),
|
||||
.por_l_in(por_l),
|
||||
.por_l_out(por_l_buf),
|
||||
|
||||
// Clock and reset
|
||||
.core_clk(caravel_clk_buf),
|
||||
.core_rstn(caravel_rstn_buf),
|
||||
|
||||
// Pass thru Clock and reset
|
||||
.clk_in(caravel_clk),
|
||||
.resetn_in(caravel_rstn),
|
||||
.clk_in(caravel_clk_buf),
|
||||
.resetn_in(caravel_rstn_buf),
|
||||
.clk_out(clk_passthru),
|
||||
.resetn_out(resetn_passthru),
|
||||
|
||||
|
|
@ -581,9 +664,10 @@ module caravan (
|
|||
.mprj_sel_o_core(mprj_sel_o_core),
|
||||
.mprj_adr_o_core(mprj_adr_o_core),
|
||||
.mprj_dat_o_core(mprj_dat_o_core),
|
||||
.mprj_dat_i_core(mprj_dat_i_core),
|
||||
.mprj_ack_i_core(mprj_ack_i_core),
|
||||
.mprj_dat_i_core(mprj_dat_i_core),
|
||||
.user_irq_core(user_irq_core),
|
||||
.user_irq_ena(user_irq_ena),
|
||||
.la_data_out_core(la_data_out_user),
|
||||
.la_data_out_mprj(la_data_out_mprj),
|
||||
.la_data_in_core(la_data_in_user),
|
||||
|
|
@ -591,7 +675,6 @@ module caravan (
|
|||
.la_oenb_mprj(la_oenb_mprj),
|
||||
.la_oenb_core(la_oenb_user),
|
||||
.la_iena_mprj(la_iena_mprj),
|
||||
.user_irq_ena(user_irq_ena),
|
||||
|
||||
.user_clock(mprj_clock),
|
||||
.user_clock2(mprj_clock2),
|
||||
|
|
@ -648,7 +731,11 @@ module caravan (
|
|||
.io_in_3v3 (user_io_in_3v3),
|
||||
.io_out(user_io_out),
|
||||
.io_oeb(user_io_oeb),
|
||||
.io_analog(user_analog),
|
||||
`ifndef TOP_ROUTING
|
||||
.io_analog(user_analog),
|
||||
.io_clamp_high(user_clamp_high),
|
||||
.io_clamp_low(user_clamp_low),
|
||||
`endif
|
||||
.gpio_analog(user_gpio_analog),
|
||||
.gpio_noesd(user_gpio_noesd),
|
||||
|
||||
|
|
@ -658,8 +745,6 @@ module caravan (
|
|||
.la_oenb(la_oenb_user),
|
||||
|
||||
// User-accessible power supply clamps
|
||||
.io_clamp_high(user_clamp_high),
|
||||
.io_clamp_low(user_clamp_low),
|
||||
|
||||
// Independent clock
|
||||
.user_clock2(mprj_clock2),
|
||||
|
|
@ -680,7 +765,7 @@ module caravan (
|
|||
mprj_io_loader_data_1};
|
||||
// Note that serial_link_2 is backwards compared to serial_link_1, so it
|
||||
// shifts in the other direction.
|
||||
assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2,
|
||||
assign gpio_serial_link_2_shifted = {mprj_io_loader_data_2_buf,
|
||||
gpio_serial_link_2[`MPRJ_IO_PADS_2
|
||||
-`ANALOG_PADS_2-1:1]};
|
||||
|
||||
|
|
@ -700,15 +785,15 @@ module caravan (
|
|||
|
||||
assign gpio_clock_1_shifted = {gpio_clock_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
|
||||
mprj_io_loader_clock};
|
||||
assign gpio_clock_2_shifted = {mprj_io_loader_clock,
|
||||
assign gpio_clock_2_shifted = {mprj_io_loader_clock_buf,
|
||||
gpio_clock_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
|
||||
assign gpio_resetn_1_shifted = {gpio_resetn_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
|
||||
mprj_io_loader_resetn};
|
||||
assign gpio_resetn_2_shifted = {mprj_io_loader_resetn,
|
||||
assign gpio_resetn_2_shifted = {mprj_io_loader_resetn_buf,
|
||||
gpio_resetn_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
|
||||
assign gpio_load_1_shifted = {gpio_load_1[`MPRJ_IO_PADS_1-`ANALOG_PADS_1-2:0],
|
||||
mprj_io_loader_strobe};
|
||||
assign gpio_load_2_shifted = {mprj_io_loader_strobe,
|
||||
assign gpio_load_2_shifted = {mprj_io_loader_strobe_buf,
|
||||
gpio_load_2[`MPRJ_IO_PADS_2-`ANALOG_PADS_2-1:1]};
|
||||
|
||||
wire [2:0] spi_pll_sel;
|
||||
|
|
@ -724,10 +809,10 @@ module caravan (
|
|||
.VGND(vssd_core),
|
||||
`endif
|
||||
.ext_clk_sel(ext_clk_sel),
|
||||
.ext_clk(clock_core),
|
||||
.ext_clk(clock_core_buf),
|
||||
.pll_clk(pll_clk),
|
||||
.pll_clk90(pll_clk90),
|
||||
.resetb(rstb_l),
|
||||
.resetb(rstb_l_buf),
|
||||
.sel(spi_pll_sel),
|
||||
.sel2(spi_pll90_sel),
|
||||
.ext_reset(ext_reset), // From housekeeping SPI
|
||||
|
|
@ -743,9 +828,9 @@ module caravan (
|
|||
.VPWR(vccd_core),
|
||||
.VGND(vssd_core),
|
||||
`endif
|
||||
.resetb(rstb_l),
|
||||
.resetb(rstb_l_buf),
|
||||
.enable(spi_pll_ena),
|
||||
.osc(clock_core),
|
||||
.osc(clock_core_buf),
|
||||
.clockp({pll_clk, pll_clk90}),
|
||||
.div(spi_pll_div),
|
||||
.dco(spi_pll_dco_ena),
|
||||
|
|
@ -846,8 +931,8 @@ module caravan (
|
|||
.pad_flash_io1_ieb(flash_io1_ieb),
|
||||
.pad_flash_io0_do(flash_io0_do),
|
||||
.pad_flash_io1_do(flash_io1_do),
|
||||
.pad_flash_io0_di(flash_io0_di),
|
||||
.pad_flash_io1_di(flash_io1_di),
|
||||
.pad_flash_io0_di(flash_io0_di_buf),
|
||||
.pad_flash_io1_di(flash_io1_di_buf),
|
||||
|
||||
`ifdef USE_SRAM_RO_INTERFACE
|
||||
.sram_ro_clk(hkspi_sram_clk),
|
||||
|
|
@ -1485,5 +1570,15 @@ module caravan (
|
|||
.spare_xfqn(spare_xfqn_nc)
|
||||
);
|
||||
|
||||
`ifdef TOP_ROUTING
|
||||
caravan_power_routing caravan_power_routing();
|
||||
caravan_signal_routing caravan_signal_routing();
|
||||
caravan_motto caravan_motto();
|
||||
caravan_logo caravan_logo();
|
||||
copyright_block_a copyright_block_a();
|
||||
user_id_textblock user_id_textblock();
|
||||
open_source open_source();
|
||||
`endif
|
||||
|
||||
endmodule
|
||||
// `default_nettype wire
|
||||
|
|
|
|||
|
|
@ -0,0 +1,2 @@
|
|||
module caravan_power_routing ();
|
||||
endmodule
|
||||
|
|
@ -91,8 +91,6 @@ module chip_io_alt #(
|
|||
input flash_clk_oeb_core,
|
||||
input flash_io0_oeb_core,
|
||||
input flash_io1_oeb_core,
|
||||
input flash_csb_ieb_core,
|
||||
input flash_clk_ieb_core,
|
||||
input flash_io0_ieb_core,
|
||||
input flash_io1_ieb_core,
|
||||
input flash_io0_do_core,
|
||||
|
|
@ -372,7 +370,7 @@ module chip_io_alt #(
|
|||
// free reset.
|
||||
|
||||
wire xresloop;
|
||||
wire xres_zero_loop
|
||||
wire xres_zero_loop;
|
||||
sky130_fd_io__top_xres4v2 resetb_pad (
|
||||
`MGMT_ABUTMENT_PINS
|
||||
`ifndef TOP_ROUTING
|
||||
|
|
|
|||
Loading…
Reference in New Issue