mirror of https://github.com/efabless/caravel.git
reharden spare_logic_block.
This commit is contained in:
mo-hosni
parent
3f29ea49e7
commit
e560b56db5
File diff suppressed because it is too large
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@ -344,16 +344,8 @@ MACRO spare_logic_block
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END
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END spare_xz[9]
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PIN vccd
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DIRECTION INPUT ;
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DIRECTION INOUT ;
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USE POWER ;
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PORT
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LAYER met5 ;
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RECT 5.520 6.400 39.100 8.000 ;
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END
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PORT
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LAYER met5 ;
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RECT 5.520 26.400 39.100 28.000 ;
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END
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PORT
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LAYER met4 ;
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RECT 5.720 5.200 7.320 38.320 ;
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@ -364,12 +356,8 @@ MACRO spare_logic_block
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END
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END vccd
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PIN vssd
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DIRECTION INPUT ;
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DIRECTION INOUT ;
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USE GROUND ;
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PORT
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LAYER met5 ;
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RECT 5.520 16.400 39.100 18.000 ;
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END
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PORT
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LAYER met4 ;
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RECT 15.720 5.200 17.320 38.320 ;
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@ -381,9 +369,9 @@ MACRO spare_logic_block
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END vssd
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OBS
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LAYER li1 ;
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RECT 5.520 0.425 39.875 41.055 ;
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RECT 5.520 5.355 39.100 38.165 ;
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LAYER met1 ;
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RECT 0.070 0.380 42.250 41.100 ;
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RECT 0.070 5.200 42.250 38.320 ;
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LAYER met2 ;
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RECT 0.650 40.720 3.030 44.725 ;
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RECT 3.870 40.720 9.470 44.725 ;
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@ -0,0 +1,292 @@
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library (spare_logic_block) {
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comment : "";
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delay_model : table_lookup;
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simulation : false;
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capacitive_load_unit (1,pF);
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leakage_power_unit : 1pW;
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current_unit : "1A";
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pulling_resistance_unit : "1kohm";
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time_unit : "1ns";
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voltage_unit : "1v";
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library_features(report_delay_calculation);
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input_threshold_pct_rise : 50;
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input_threshold_pct_fall : 50;
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output_threshold_pct_rise : 50;
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output_threshold_pct_fall : 50;
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slew_lower_threshold_pct_rise : 20;
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slew_lower_threshold_pct_fall : 20;
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slew_upper_threshold_pct_rise : 80;
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slew_upper_threshold_pct_fall : 80;
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slew_derate_from_library : 1.0;
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nom_process : 1.0;
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nom_temperature : 25.0;
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nom_voltage : 1.80;
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type ("spare_xfq") {
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base_type : array;
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data_type : bit;
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bit_width : 2;
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bit_from : 1;
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bit_to : 0;
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}
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type ("spare_xfqn") {
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base_type : array;
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data_type : bit;
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bit_width : 2;
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bit_from : 1;
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bit_to : 0;
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}
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type ("spare_xi") {
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base_type : array;
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data_type : bit;
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bit_width : 4;
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bit_from : 3;
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bit_to : 0;
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}
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type ("spare_xmx") {
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base_type : array;
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data_type : bit;
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bit_width : 2;
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bit_from : 1;
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bit_to : 0;
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}
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type ("spare_xna") {
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base_type : array;
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data_type : bit;
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bit_width : 2;
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bit_from : 1;
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bit_to : 0;
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}
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type ("spare_xno") {
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base_type : array;
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data_type : bit;
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bit_width : 2;
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bit_from : 1;
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bit_to : 0;
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}
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type ("spare_xz") {
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base_type : array;
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data_type : bit;
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bit_width : 27;
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bit_from : 26;
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bit_to : 0;
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}
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cell ("spare_logic_block") {
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pin("spare_xib") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("vccd") {
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direction : input;
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capacitance : 0.0000;
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}
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pin("vssd") {
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direction : input;
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capacitance : 0.0000;
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}
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bus("spare_xfq") {
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bus_type : spare_xfq;
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direction : output;
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capacitance : 0.0000;
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pin("spare_xfq[1]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xfq[0]") {
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direction : output;
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capacitance : 0.0334;
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}
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}
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bus("spare_xfqn") {
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bus_type : spare_xfqn;
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direction : output;
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capacitance : 0.0000;
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pin("spare_xfqn[1]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xfqn[0]") {
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direction : output;
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capacitance : 0.0334;
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}
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}
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bus("spare_xi") {
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bus_type : spare_xi;
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direction : output;
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capacitance : 0.0000;
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pin("spare_xi[3]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xi[2]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xi[1]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xi[0]") {
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direction : output;
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capacitance : 0.0334;
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}
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}
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bus("spare_xmx") {
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bus_type : spare_xmx;
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direction : output;
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capacitance : 0.0000;
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pin("spare_xmx[1]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xmx[0]") {
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direction : output;
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capacitance : 0.0334;
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}
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}
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bus("spare_xna") {
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bus_type : spare_xna;
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direction : output;
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capacitance : 0.0000;
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pin("spare_xna[1]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xna[0]") {
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direction : output;
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capacitance : 0.0334;
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}
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}
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bus("spare_xno") {
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bus_type : spare_xno;
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direction : output;
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capacitance : 0.0000;
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pin("spare_xno[1]") {
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direction : output;
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capacitance : 0.0334;
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}
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pin("spare_xno[0]") {
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direction : output;
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capacitance : 0.0334;
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}
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}
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bus("spare_xz") {
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bus_type : spare_xz;
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direction : output;
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capacitance : 0.0000;
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pin("spare_xz[26]") {
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direction : output;
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capacitance : 0.0351;
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}
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pin("spare_xz[25]") {
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direction : output;
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capacitance : 0.0351;
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}
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pin("spare_xz[24]") {
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direction : output;
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capacitance : 0.0369;
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}
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pin("spare_xz[23]") {
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direction : output;
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capacitance : 0.0369;
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}
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pin("spare_xz[22]") {
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direction : output;
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capacitance : 0.0353;
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}
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pin("spare_xz[21]") {
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direction : output;
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capacitance : 0.0353;
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}
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pin("spare_xz[20]") {
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direction : output;
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capacitance : 0.0351;
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}
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pin("spare_xz[19]") {
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direction : output;
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capacitance : 0.0351;
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}
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pin("spare_xz[18]") {
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direction : output;
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capacitance : 0.0368;
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}
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pin("spare_xz[17]") {
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direction : output;
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capacitance : 0.0368;
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}
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pin("spare_xz[16]") {
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direction : output;
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capacitance : 0.0352;
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}
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pin("spare_xz[15]") {
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direction : output;
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capacitance : 0.0352;
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}
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pin("spare_xz[14]") {
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direction : output;
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capacitance : 0.0354;
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}
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pin("spare_xz[13]") {
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direction : output;
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capacitance : 0.0354;
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}
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pin("spare_xz[12]") {
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direction : output;
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capacitance : 0.0381;
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}
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pin("spare_xz[11]") {
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direction : output;
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capacitance : 0.0381;
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}
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pin("spare_xz[10]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[9]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[8]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[7]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[6]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[5]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[4]") {
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direction : output;
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capacitance : 0.0519;
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}
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pin("spare_xz[3]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[2]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[1]") {
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direction : output;
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capacitance : 0.0380;
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}
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pin("spare_xz[0]") {
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direction : output;
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capacitance : 0.0380;
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}
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}
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}
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}
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File diff suppressed because it is too large
Load Diff
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@ -1,11 +1,11 @@
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magic
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tech sky130A
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magscale 1 2
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timestamp 1637778834
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timestamp 1677507642
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<< obsli1 >>
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rect 1104 85 7975 8211
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rect 1104 1071 7820 7633
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<< obsm1 >>
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rect 14 76 8450 8220
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rect 14 1040 8450 7664
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<< metal2 >>
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rect 18 8200 74 9000
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rect 662 8200 718 9000
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@ -105,10 +105,6 @@ rect 1144 1040 1464 7664
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rect 3144 1040 3464 7664
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rect 5144 1040 5464 7664
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rect 7144 1040 7464 7664
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<< metal5 >>
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rect 1104 5280 7820 5600
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rect 1104 3280 7820 3600
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rect 1104 1280 7820 1600
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<< labels >>
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rlabel metal3 s 0 2048 800 2168 6 spare_xfq[0]
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port 1 nsew signal output
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@ -194,26 +190,20 @@ rlabel metal3 s 0 8848 800 8968 6 spare_xz[8]
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port 41 nsew signal output
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rlabel metal3 s 8200 4088 9000 4208 6 spare_xz[9]
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port 42 nsew signal output
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rlabel metal5 s 1104 1280 7820 1600 6 vccd
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port 43 nsew power input
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rlabel metal5 s 1104 5280 7820 5600 6 vccd
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port 43 nsew power input
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rlabel metal4 s 1144 1040 1464 7664 6 vccd
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port 43 nsew power input
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port 43 nsew power bidirectional
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rlabel metal4 s 5144 1040 5464 7664 6 vccd
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port 43 nsew power input
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rlabel metal5 s 1104 3280 7820 3600 6 vssd
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port 44 nsew ground input
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port 43 nsew power bidirectional
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rlabel metal4 s 3144 1040 3464 7664 6 vssd
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port 44 nsew ground input
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port 44 nsew ground bidirectional
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rlabel metal4 s 7144 1040 7464 7664 6 vssd
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port 44 nsew ground input
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port 44 nsew ground bidirectional
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<< properties >>
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string LEFclass BLOCK
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string FIXED_BBOX 0 0 9000 9000
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string LEFclass BLOCK
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string LEFview TRUE
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string GDS_FILE ../gds/spare_logic_block.gds
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string GDS_END 175312
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string GDS_START 71630
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string GDS_END 176778
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string GDS_FILE /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.magic.gds
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string GDS_START 71278
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<< end >>
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@ -15,7 +15,7 @@
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# This is an analog design. It will be designed by hand.
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# This is a placeholder to get things going.
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set script_dir [file dirname [file normalize [info script]]]
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set script_dir $::env(DESIGN_DIR)
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set ::env(DESIGN_NAME) spare_logic_block
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@ -25,6 +25,7 @@ set ::env(VERILOG_FILES_BLACKBOX) $script_dir/../../verilog/stubs/sky130_fd_sc_h
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set ::env(CLOCK_PORT) ""
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set ::env(CLOCK_TREE_SYNTH) 0
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set ::env(DESIGN_IS_CORE) 0
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## Synthesis
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set ::env(SYNTH_READ_BLACKBOX_LIB) 1
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@ -55,4 +56,4 @@ set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) 0
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set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) 0
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## Routing
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
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set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) 0
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@ -1 +1 @@
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openlane 2021.11.23_01.42.34
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OpenLane 1ed36219093ce86ddbc1b981e461c5f38e5bba72
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@ -1,3 +1 @@
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openlane cbb562bd43c5c410b1b498604803c3dd88a44856
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skywater-pdk c094b6e83a4f9298e47f696ec5a7fd53535ec5eb
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open_pdks c5730b574461889c82858b08d12ba42423d9c2cb
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open_pdks 327e268bdb7191fe07a28bd40eeac055bba9dffd
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@ -0,0 +1,130 @@
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Mon Feb 27 14:20:21 UTC 2023 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/lefutil.py get_metal_layers -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/layers.list /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef"
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Mon Feb 27 14:20:22 UTC 2023 - Executing "/openlane/scripts/mergeLef.py -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.nom.lef -i /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef} |& tee /dev/null"
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Mon Feb 27 14:20:22 UTC 2023 - Executing "/openlane/scripts/mergeLef.py -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.min.lef -i /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef} |& tee /dev/null"
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|
||||
Mon Feb 27 14:20:22 UTC 2023 - Executing "/openlane/scripts/mergeLef.py -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.max.lef -i /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef} |& tee /dev/null"
|
||||
|
||||
Mon Feb 27 14:20:22 UTC 2023 - Executing "python3 /openlane/scripts/mergeLib.py --output /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/merged.lib --name sky130A_merged /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
|
||||
|
||||
Mon Feb 27 14:20:22 UTC 2023 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/trimmed.lib.exclude.list --output /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/trimmed.lib /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/merged.lib"
|
||||
|
||||
Mon Feb 27 14:20:22 UTC 2023 - Executing "python3 /openlane/scripts/libtrim.py --cell-file /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/cts/cts.lib.exclude.list --output /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/cts/cts.lib /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib"
|
||||
|
||||
Mon Feb 27 14:20:23 UTC 2023 - Executing "python3 /openlane/scripts/new_tracks.py -i /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/routing/config.tracks"
|
||||
|
||||
Mon Feb 27 14:20:23 UTC 2023 - Executing "echo {OpenLane 1ed36219093ce86ddbc1b981e461c5f38e5bba72} > /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/OPENLANE_VERSION"
|
||||
|
||||
Mon Feb 27 14:20:23 UTC 2023 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib > /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/1-sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib"
|
||||
|
||||
Mon Feb 27 14:20:23 UTC 2023 - Executing "sed -E {s/^([[:space:]]+)pg_pin(.*)/\1pin\2\n\1 direction : "inout";/g} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/trimmed.lib > /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/1-trimmed.no_pg.lib"
|
||||
|
||||
Mon Feb 27 14:20:23 UTC 2023 - Executing "yosys -c /openlane/scripts/yosys/synth.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/synthesis/1-synthesis.log"
|
||||
|
||||
Mon Feb 27 14:20:24 UTC 2023 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/hosni\/caravel_sky130\/caravel_redesign-2\/caravel\/openlane\/spare_logic_block\/runs\/23_02_27_06_20\/results\/synthesis\/spare_logic_block.v/} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl"
|
||||
|
||||
Mon Feb 27 14:20:24 UTC 2023 - Executing "sed -i /defparam/d /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/synthesis/spare_logic_block.v"
|
||||
|
||||
Mon Feb 27 14:20:24 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/synthesis/2-sta.log"
|
||||
|
||||
Mon Feb 27 14:20:25 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/floorplan.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/floorplan/3-initial_fp.log"
|
||||
|
||||
Mon Feb 27 14:20:25 UTC 2023 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/defutil.py extract_core_dims --output-data /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/dimensions.txt --input-lef /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.nom.lef /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/floorplan/3-initial_fp.def"
|
||||
|
||||
Mon Feb 27 14:20:26 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/ioplacer.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/floorplan/4-io.log"
|
||||
|
||||
Mon Feb 27 14:20:26 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/tapcell.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/floorplan/5-tap.log"
|
||||
|
||||
Mon Feb 27 14:20:27 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/pdn.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/floorplan/6-pdn.log"
|
||||
|
||||
Mon Feb 27 14:20:27 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/gpl.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/placement/7-global.log"
|
||||
|
||||
Mon Feb 27 14:20:28 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/placement/8-detailed.log"
|
||||
|
||||
Mon Feb 27 14:20:28 UTC 2023 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/hosni\/caravel_sky130\/caravel_redesign-2\/caravel\/openlane\/spare_logic_block\/runs\/23_02_27_06_20\/results\/placement\/spare_logic_block.nl.v/} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl"
|
||||
|
||||
Mon Feb 27 14:20:29 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/dpl.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing/9-diode_legalization.log"
|
||||
|
||||
Mon Feb 27 14:20:29 UTC 2023 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/hosni\/caravel_sky130\/caravel_redesign-2\/caravel\/openlane\/spare_logic_block\/runs\/23_02_27_06_20\/tmp\/routing\/diode.nl.v/} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl"
|
||||
|
||||
Mon Feb 27 14:20:29 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/groute.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing/10-global.log"
|
||||
|
||||
Mon Feb 27 14:20:30 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing/10-global_write_netlist.log"
|
||||
|
||||
Mon Feb 27 14:20:30 UTC 2023 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/hosni\/caravel_sky130\/caravel_redesign-2\/caravel\/openlane\/spare_logic_block\/runs\/23_02_27_06_20\/tmp\/routing\/global.nl.v/} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl"
|
||||
|
||||
Mon Feb 27 14:20:30 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/fill.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing/12-fill.log"
|
||||
|
||||
Mon Feb 27 14:20:31 UTC 2023 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/hosni\/caravel_sky130\/caravel_redesign-2\/caravel\/openlane\/spare_logic_block\/runs\/23_02_27_06_20\/tmp\/routing\/12-fill.nl.v/} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl"
|
||||
|
||||
Mon Feb 27 14:20:31 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/droute.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing/13-detailed.log"
|
||||
|
||||
Mon Feb 27 14:20:33 UTC 2023 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/hosni\/caravel_sky130\/caravel_redesign-2\/caravel\/openlane\/spare_logic_block\/runs\/23_02_27_06_20\/results\/routing\/spare_logic_block.nl.v/} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl"
|
||||
|
||||
Mon Feb 27 14:20:33 UTC 2023 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/routing/drt.klayout.xml --design-name spare_logic_block /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/routing/drt.drc"
|
||||
|
||||
Mon Feb 27 14:20:33 UTC 2023 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/wire_lengths.py --report-out /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/routing/14-wire_lengths.csv --input-lef /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.nom.lef --output-def /dev/null --output /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.odb /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.odb |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing/14-wire_lengths.log"
|
||||
|
||||
Mon Feb 27 14:20:33 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/15-parasitics_extraction.min.log"
|
||||
|
||||
Mon Feb 27 14:20:34 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/16-rcx_mcsta.min.log"
|
||||
|
||||
Mon Feb 27 14:20:35 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/17-parasitics_extraction.max.log"
|
||||
|
||||
Mon Feb 27 14:20:36 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/18-rcx_mcsta.max.log"
|
||||
|
||||
Mon Feb 27 14:20:38 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/rcx.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/19-parasitics_extraction.nom.log"
|
||||
|
||||
Mon Feb 27 14:20:38 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/sta_multi_corner.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/20-rcx_mcsta.nom.log"
|
||||
|
||||
Mon Feb 27 14:20:40 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/sta.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/21-rcx_sta.log"
|
||||
|
||||
Mon Feb 27 14:20:40 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/irdrop.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/22-irdrop.log"
|
||||
|
||||
Mon Feb 27 14:20:41 UTC 2023 - Executing "magic -noconsole -dnull -rcfile /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc < /openlane/scripts/magic/def/mag_gds.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/23-gdsii.log"
|
||||
|
||||
Mon Feb 27 14:20:41 UTC 2023 - Executing "magic -noconsole -dnull -rcfile /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc < /openlane/scripts/magic/gds/mag_with_pointers.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/23-gds_ptrs.log"
|
||||
|
||||
Mon Feb 27 14:20:42 UTC 2023 - Executing "sed -i -n {/^<< properties >>/,/^<< end >>/p} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/gds_ptrs.mag"
|
||||
|
||||
Mon Feb 27 14:20:42 UTC 2023 - Executing "magic -noconsole -dnull -rcfile /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc < /openlane/scripts/magic/mag/lef.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/23-lef.log"
|
||||
|
||||
Mon Feb 27 14:20:42 UTC 2023 - Executing "magic -noconsole -dnull -rcfile /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc < /openlane/scripts/magic/lef/maglef.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/23-maglef.log"
|
||||
|
||||
Mon Feb 27 14:20:42 UTC 2023 - Executing "python3 /openlane/scripts/klayout/stream_out.py --output /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.klayout.gds --tech-file /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyt --props-file /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp --top spare_logic_block --with-gds-file /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds --input-lef /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.nom.lef /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.def |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/24-gdsii-klayout.log"
|
||||
|
||||
Mon Feb 27 14:20:43 UTC 2023 - Executing "klayout -b -r /openlane/scripts/klayout/xor.drc -rd a=/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.gds -rd b=/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.klayout.gds -rd jobs=1 -rd rdb_out=/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/25-xor.xml -rd rpt_out=/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/25-xor.rpt |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/25-xor.log"
|
||||
|
||||
Mon Feb 27 14:20:43 UTC 2023 - Executing "magic -noconsole -dnull -rcfile /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc < /openlane/scripts/magic/extract_spice.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/26-spice.log"
|
||||
|
||||
Mon Feb 27 14:20:44 UTC 2023 - Executing "openroad -exit -no_init -python /openlane/scripts/odbpy/power_utils.py write_powered_def --output /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.p.def --input-lef /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.nom.lef --power-port vccd --ground-port vssd --powered-netlist {} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.def |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/27-write_powered_def.log"
|
||||
|
||||
Mon Feb 27 14:20:44 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/write_views.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/27-write_powered_verilog.log"
|
||||
|
||||
Mon Feb 27 14:20:45 UTC 2023 - Executing "sed -i -e {s/\(set ::env(CURRENT_NETLIST)\).*/\1 \/home\/hosni\/caravel_sky130\/caravel_redesign-2\/caravel\/openlane\/spare_logic_block\/runs\/23_02_27_06_20\/tmp\/signoff\/26-spare_logic_block.nl.v/} /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl"
|
||||
|
||||
Mon Feb 27 14:20:45 UTC 2023 - Executing "netgen -batch source /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/29-setup_file.lef.lvs |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/29-lvs.lef.log"
|
||||
|
||||
Mon Feb 27 14:20:45 UTC 2023 - Executing "magic -noconsole -dnull -rcfile /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc < /openlane/scripts/magic/drc.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/30-drc.log"
|
||||
|
||||
Mon Feb 27 14:20:46 UTC 2023 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tcl -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.tcl /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.rpt"
|
||||
|
||||
Mon Feb 27 14:20:46 UTC 2023 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_tr -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.tr /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.rpt"
|
||||
|
||||
Mon Feb 27 14:20:46 UTC 2023 - Executing "python3 /openlane/scripts/drc_rosetta.py tr to_klayout -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.klayout.xml --design-name spare_logic_block /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.tr"
|
||||
|
||||
Mon Feb 27 14:20:46 UTC 2023 - Executing "python3 /openlane/scripts/drc_rosetta.py magic to_rdb -o /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.rdb /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.rpt"
|
||||
|
||||
Mon Feb 27 14:20:46 UTC 2023 - Executing "openroad -exit /openlane/scripts/openroad/antenna_check.tcl |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/31-antenna.log"
|
||||
|
||||
Mon Feb 27 14:20:47 UTC 2023 - Executing "python3 /openlane/scripts/extract_antenna_violators.py --output /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/31-antenna_violators.rpt /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/31-antenna.log"
|
||||
|
||||
Mon Feb 27 14:20:47 UTC 2023 - Executing "awk -v vdd=vccd -v gnd=vssd -f /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/cvc/power.awk /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.nl.v > /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/spare_logic_block.power"
|
||||
|
||||
Mon Feb 27 14:20:47 UTC 2023 - Executing "awk -f /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/cvc/cdl.awk /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.lef.spice > /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/spare_logic_block.cdl"
|
||||
|
||||
Mon Feb 27 14:20:47 UTC 2023 - Executing "cvc_rv /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/cvc/cvcrc |& tee /dev/null /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/32-erc_screen.log"
|
||||
|
||||
Mon Feb 27 14:20:47 UTC 2023 - Executing "python3 /openlane/scripts/generate_reports.py -d /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block --design_name spare_logic_block --tag 23_02_27_06_20 --output_file /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/metrics.csv --man_report /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/manufacturability.rpt --run_path /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20"
|
||||
|
||||
|
|
@ -0,0 +1,762 @@
|
|||
# Run configs
|
||||
set ::env(PDK_ROOT) {/home/hosni/swift/OpenLane/pdks}
|
||||
set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
|
||||
set ::env(BOTTOM_MARGIN_MULT) {2}
|
||||
set ::env(CARRY_SELECT_ADDER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v}
|
||||
set ::env(CELLS_LEF) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELLS_LEF_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELL_CLK_PORT) {CLK}
|
||||
set ::env(CELL_PAD_EXCLUDE) {sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*}
|
||||
set ::env(CHECK_ASSIGN_STATEMENTS) {0}
|
||||
set ::env(CHECK_UNMAPPED_CELLS) {1}
|
||||
set ::env(CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_4}
|
||||
set ::env(CLK_BUFFER_INPUT) {A}
|
||||
set ::env(CLK_BUFFER_OUTPUT) {X}
|
||||
set ::env(CLOCK_BUFFER_FANOUT) {16}
|
||||
set ::env(CLOCK_PERIOD) {10.0}
|
||||
set ::env(CLOCK_PORT) {}
|
||||
set ::env(CLOCK_TREE_SYNTH) {0}
|
||||
set ::env(CLOCK_WIRE_RC_LAYER) {met5}
|
||||
set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
|
||||
set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2}
|
||||
set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(CTS_DISABLE_POST_PROCESSING) {0}
|
||||
set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
|
||||
set ::env(CTS_MAX_CAP) {1.53169}
|
||||
set ::env(CTS_REPORT_TIMING) {1}
|
||||
set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
|
||||
set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
|
||||
set ::env(CTS_SQR_CAP) {0.258e-3}
|
||||
set ::env(CTS_SQR_RES) {0.125}
|
||||
set ::env(CTS_TARGET_SKEW) {200}
|
||||
set ::env(CTS_TECH_DIR) {N/A}
|
||||
set ::env(CTS_TOLERANCE) {100}
|
||||
set ::env(CVC_SCRIPTS_DIR) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/cvc}
|
||||
set ::env(DATA_WIRE_RC_LAYER) {met2}
|
||||
set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
|
||||
set ::env(DEFAULT_MAX_TRAN) {0.75}
|
||||
set ::env(DEF_UNITS_PER_MICRON) {1000}
|
||||
set ::env(DESIGN_CONFIG) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/config.tcl}
|
||||
set ::env(DESIGN_IS_CORE) {0}
|
||||
set ::env(DESIGN_NAME) {spare_logic_block}
|
||||
set ::env(DETAILED_ROUTER) {tritonroute}
|
||||
set ::env(DIE_AREA) {0 0 45 45}
|
||||
set ::env(DIODE_CELL) {sky130_fd_sc_hd__diode_2}
|
||||
set ::env(DIODE_CELL_PIN) {DIODE}
|
||||
set ::env(DIODE_INSERTION_STRATEGY) {3}
|
||||
set ::env(DIODE_PADDING) {2}
|
||||
set ::env(DPL_CELL_PADDING) {4}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
|
||||
set ::env(DRT_OPT_ITERS) {64}
|
||||
set ::env(ECO_ENABLE) {0}
|
||||
set ::env(ECO_FINISH) {0}
|
||||
set ::env(ECO_ITER) {0}
|
||||
set ::env(ECO_SKIP_PIN) {1}
|
||||
set ::env(FAKEDIODE_CELL) {sky130_ef_sc_hd__fakediode_2}
|
||||
set ::env(FILL_CELL) {sky130_fd_sc_hd__fill*}
|
||||
set ::env(FP_ASPECT_RATIO) {1}
|
||||
set ::env(FP_CORE_UTIL) {50}
|
||||
set ::env(FP_ENDCAP_CELL) {sky130_fd_sc_hd__decap_3}
|
||||
set ::env(FP_IO_HEXTEND) {0}
|
||||
set ::env(FP_IO_HLAYER) {met3}
|
||||
set ::env(FP_IO_HLENGTH) {4}
|
||||
set ::env(FP_IO_HTHICKNESS_MULT) {2}
|
||||
set ::env(FP_IO_MIN_DISTANCE) {3}
|
||||
set ::env(FP_IO_MODE) {1}
|
||||
set ::env(FP_IO_UNMATCHED_ERROR) {1}
|
||||
set ::env(FP_IO_VEXTEND) {0}
|
||||
set ::env(FP_IO_VLAYER) {met2}
|
||||
set ::env(FP_IO_VLENGTH) {4}
|
||||
set ::env(FP_IO_VTHICKNESS_MULT) {2}
|
||||
set ::env(FP_PDN_AUTO_ADJUST) {0}
|
||||
set ::env(FP_PDN_CHECK_NODES) {1}
|
||||
set ::env(FP_PDN_CORE_RING) {0}
|
||||
set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
|
||||
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
|
||||
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
|
||||
set ::env(FP_PDN_ENABLE_RAILS) {1}
|
||||
set ::env(FP_PDN_HOFFSET) {2}
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_PDN_HPITCH) {20}
|
||||
set ::env(FP_PDN_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_IRDROP) {1}
|
||||
set ::env(FP_PDN_LOWER_LAYER) {met4}
|
||||
set ::env(FP_PDN_RAILS_LAYER) {met1}
|
||||
set ::env(FP_PDN_RAIL_OFFSET) {0}
|
||||
set ::env(FP_PDN_RAIL_WIDTH) {0.48}
|
||||
set ::env(FP_PDN_SKIPTRIM) {0}
|
||||
set ::env(FP_PDN_UPPER_LAYER) {met5}
|
||||
set ::env(FP_PDN_VERTICAL_HALO) {10}
|
||||
set ::env(FP_PDN_VOFFSET) {1}
|
||||
set ::env(FP_PDN_VPITCH) {20}
|
||||
set ::env(FP_PDN_VSPACING) {1.7}
|
||||
set ::env(FP_PDN_VWIDTH) {1.6}
|
||||
set ::env(FP_SIZING) {absolute}
|
||||
set ::env(FP_TAPCELL_DIST) {13}
|
||||
set ::env(FP_TAP_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_TAP_VERTICAL_HALO) {10}
|
||||
set ::env(FP_WELLTAP_CELL) {sky130_fd_sc_hd__tapvpwrvgnd_1}
|
||||
set ::env(FULL_ADDER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v}
|
||||
set ::env(GDS_FILES) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GDS_FILES_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
|
||||
set ::env(GLB_CFG_FILE) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl}
|
||||
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
|
||||
set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(GLOBAL_ROUTER) {fastroute}
|
||||
set ::env(GND_NETS) {vssd}
|
||||
set ::env(GND_PIN) {VGND}
|
||||
set ::env(GPIO_PADS_LEF) { /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef }
|
||||
set ::env(GPIO_PADS_LEF_CORE_SIDE) { /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef }
|
||||
set ::env(GPIO_PADS_PREFIX) {sky130_fd_io sky130_ef_io}
|
||||
set ::env(GPIO_PADS_VERILOG) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/verilog/sky130_fd_io/sky130_ef_io.v}
|
||||
set ::env(GPL_CELL_PADDING) {0}
|
||||
set ::env(GRT_ADJUSTMENT) {0.3}
|
||||
set ::env(GRT_ALLOW_CONGESTION) {0}
|
||||
set ::env(GRT_ANT_ITERS) {3}
|
||||
set ::env(GRT_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(GRT_LAYER_ADJUSTMENTS) {0.99,0,0,0,0,0}
|
||||
set ::env(GRT_MACRO_EXTENSION) {0}
|
||||
set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
|
||||
set ::env(GRT_OVERFLOW_ITERS) {50}
|
||||
set ::env(IO_PCT) {0.2}
|
||||
set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
|
||||
set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/drc/sky130A_mr.drc}
|
||||
set ::env(KLAYOUT_PROPERTIES) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp}
|
||||
set ::env(KLAYOUT_TECH) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyt}
|
||||
set ::env(KLAYOUT_XOR_GDS) {1}
|
||||
set ::env(KLAYOUT_XOR_THREADS) {1}
|
||||
set ::env(KLAYOUT_XOR_XML) {1}
|
||||
set ::env(LEC_ENABLE) {0}
|
||||
set ::env(LEFT_MARGIN_MULT) {12}
|
||||
set ::env(LIB_FASTEST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib}
|
||||
set ::env(LIB_SLOWEST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SLOWEST_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SYNTH) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LIB_TYPICAL) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LOGS_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs}
|
||||
set ::env(LVS_CONNECT_BY_LABEL) {0}
|
||||
set ::env(LVS_INSERT_POWER_PINS) {1}
|
||||
set ::env(MACRO_BLOCKAGES_LAYER) {li1 met1 met2 met3 met4}
|
||||
set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
|
||||
set ::env(MAGIC_DEF_LABELS) {1}
|
||||
set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
|
||||
set ::env(MAGIC_DISABLE_HIER_GDS) {1}
|
||||
set ::env(MAGIC_DRC_USE_GDS) {1}
|
||||
set ::env(MAGIC_EXT_USE_GDS) {0}
|
||||
set ::env(MAGIC_GDS_ALLOW_ABSTRACT) {0}
|
||||
set ::env(MAGIC_GDS_POLYGON_SUBCELLS) {0}
|
||||
set ::env(MAGIC_GENERATE_GDS) {1}
|
||||
set ::env(MAGIC_GENERATE_LEF) {1}
|
||||
set ::env(MAGIC_GENERATE_MAGLEF) {1}
|
||||
set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
|
||||
set ::env(MAGIC_MAGICRC) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc}
|
||||
set ::env(MAGIC_PAD) {0}
|
||||
set ::env(MAGIC_TECH_FILE) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech}
|
||||
set ::env(MAGIC_WRITE_FULL_LEF) {0}
|
||||
set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
|
||||
set ::env(NETGEN_SETUP_FILE) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl}
|
||||
set ::env(NO_SYNTH_CELL_LIST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells}
|
||||
set ::env(OPENLANE_VERBOSE) {1}
|
||||
set ::env(PDKPATH) {/home/hosni/swift/OpenLane/pdks/sky130A}
|
||||
set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
|
||||
set ::env(PLACE_SITE) {unithd}
|
||||
set ::env(PLACE_SITE_HEIGHT) {2.720}
|
||||
set ::env(PLACE_SITE_WIDTH) {0.460}
|
||||
set ::env(PL_BASIC_PLACEMENT) {0}
|
||||
set ::env(PL_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(PL_LIB) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(PL_MACRO_CHANNEL) {0 0}
|
||||
set ::env(PL_MACRO_HALO) {0 0}
|
||||
set ::env(PL_MAX_DISPLACEMENT_X) {500}
|
||||
set ::env(PL_MAX_DISPLACEMENT_Y) {100}
|
||||
set ::env(PL_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
|
||||
set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
|
||||
set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
|
||||
set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
|
||||
set ::env(PL_RESIZER_TIE_SEPERATION) {0}
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_ROUTABILITY_DRIVEN) {1}
|
||||
set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_TARGET_DENSITY) {0.45}
|
||||
set ::env(PL_TIME_DRIVEN) {1}
|
||||
set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
|
||||
set ::env(PROCESS) {130}
|
||||
set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
|
||||
set ::env(QUIT_ON_LONG_WIRE) {0}
|
||||
set ::env(QUIT_ON_LVS_ERROR) {1}
|
||||
set ::env(QUIT_ON_MAGIC_DRC) {1}
|
||||
set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TR_DRC) {1}
|
||||
set ::env(QUIT_ON_XOR_ERROR) {0}
|
||||
set ::env(RCX_CC_MODEL) {10}
|
||||
set ::env(RCX_CONTEXT_DEPTH) {5}
|
||||
set ::env(RCX_CORNER_COUNT) {1}
|
||||
set ::env(RCX_COUPLING_THRESHOLD) {0.1}
|
||||
set ::env(RCX_MAX_RESISTANCE) {50}
|
||||
set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
|
||||
set ::env(RCX_RULES) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre}
|
||||
set ::env(RCX_RULES_MAX) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre}
|
||||
set ::env(RCX_RULES_MIN) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre}
|
||||
set ::env(REPORTS_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports}
|
||||
set ::env(RESULTS_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results}
|
||||
set ::env(RE_BUFFER_CELL) {sky130_fd_sc_hd__buf_4}
|
||||
set ::env(RIGHT_MARGIN_MULT) {12}
|
||||
set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v}
|
||||
set ::env(ROOT_CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(ROUTING_CORES) {2}
|
||||
set ::env(RSZ_DONT_TOUCH_RX) {$^}
|
||||
set ::env(RSZ_USE_OLD_REMOVER) {0}
|
||||
set ::env(RT_MAX_LAYER) {met5}
|
||||
set ::env(RT_MIN_LAYER) {met1}
|
||||
set ::env(RUN_CVC) {1}
|
||||
set ::env(RUN_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20}
|
||||
set ::env(RUN_DRT) {1}
|
||||
set ::env(RUN_FILL_INSERTION) {1}
|
||||
set ::env(RUN_IRDROP_REPORT) {1}
|
||||
set ::env(RUN_KLAYOUT) {1}
|
||||
set ::env(RUN_KLAYOUT_DRC) {0}
|
||||
set ::env(RUN_KLAYOUT_XOR) {1}
|
||||
set ::env(RUN_LVS) {1}
|
||||
set ::env(RUN_MAGIC) {1}
|
||||
set ::env(RUN_MAGIC_DRC) {1}
|
||||
set ::env(RUN_SPEF_EXTRACTION) {1}
|
||||
set ::env(RUN_TAG) {23_02_27_06_20}
|
||||
set ::env(RUN_TAP_DECAP_INSERTION) {1}
|
||||
set ::env(SCLPATH) {/home/hosni/swift/OpenLane/pdks/sky130A/sky130_fd_sc_hd}
|
||||
set ::env(SPEF_EXTRACTOR) {openrcx}
|
||||
set ::env(START_TIME) {2023.02.27_14.20.21}
|
||||
set ::env(STA_REPORT_POWER) {1}
|
||||
set ::env(STA_WRITE_LIB) {1}
|
||||
set ::env(STD_CELL_GROUND_PINS) {VGND VNB}
|
||||
set ::env(STD_CELL_LIBRARY) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_CDL) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_LIBRARY_OPT) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_OPT_CDL) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_POWER_PINS) {VPWR VPB}
|
||||
set ::env(SYNTH_ADDER_TYPE) {YOSYS}
|
||||
set ::env(SYNTH_BIN) {yosys}
|
||||
set ::env(SYNTH_BUFFERING) {1}
|
||||
set ::env(SYNTH_CAP_LOAD) {33.442}
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
|
||||
set ::env(SYNTH_DRIVING_CELL) {sky130_fd_sc_hd__inv_2}
|
||||
set ::env(SYNTH_DRIVING_CELL_PIN) {Y}
|
||||
set ::env(SYNTH_ELABORATE_ONLY) {0}
|
||||
set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
|
||||
set ::env(SYNTH_FLAT_TOP) {0}
|
||||
set ::env(SYNTH_LATCH_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v}
|
||||
set ::env(SYNTH_MAX_FANOUT) {10}
|
||||
set ::env(SYNTH_MIN_BUF_PORT) {sky130_fd_sc_hd__buf_2 A X}
|
||||
set ::env(SYNTH_MUX4_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v}
|
||||
set ::env(SYNTH_MUX_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v}
|
||||
set ::env(SYNTH_NO_FLAT) {0}
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) {1}
|
||||
set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
|
||||
set ::env(SYNTH_SHARE_RESOURCES) {1}
|
||||
set ::env(SYNTH_SIZING) {0}
|
||||
set ::env(SYNTH_STRATEGY) {AREA 0}
|
||||
set ::env(SYNTH_TIEHI_PORT) {sky130_fd_sc_hd__conb_1 HI}
|
||||
set ::env(SYNTH_TIELO_PORT) {sky130_fd_sc_hd__conb_1 LO}
|
||||
set ::env(SYNTH_TIMING_DERATE) {0.05}
|
||||
set ::env(TAKE_LAYOUT_SCROT) {0}
|
||||
set ::env(TECH_LEF) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TECH_LEF_MAX) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef}
|
||||
set ::env(TECH_LEF_MIN) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef}
|
||||
set ::env(TECH_LEF_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TERMINAL_OUTPUT) {/dev/null}
|
||||
set ::env(TMP_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp}
|
||||
set ::env(TOP_MARGIN_MULT) {2}
|
||||
set ::env(TRACKS_INFO_FILE) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info}
|
||||
set ::env(TRISTATE_BUFFER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v}
|
||||
set ::env(USE_ARC_ANTENNA_CHECK) {1}
|
||||
set ::env(USE_GPIO_PADS) {0}
|
||||
set ::env(VDD_NETS) {vccd}
|
||||
set ::env(VDD_PIN) {VPWR}
|
||||
set ::env(VERILOG_FILES) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/../../verilog/rtl/spare_logic_block.v}
|
||||
set ::env(VERILOG_FILES_BLACKBOX) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/../../verilog/stubs/sky130_fd_sc_hd__tapvpwrvgnd_1.v}
|
||||
set ::env(WIRE_RC_LAYER) {met1}
|
||||
set ::env(YOSYS_REWRITE_VERILOG) {0}
|
||||
set ::env(cts_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/cts}
|
||||
set ::env(cts_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/cts}
|
||||
set ::env(cts_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/cts}
|
||||
set ::env(cts_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/cts}
|
||||
set ::env(eco_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/eco}
|
||||
set ::env(eco_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/eco}
|
||||
set ::env(eco_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/eco}
|
||||
set ::env(eco_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/eco}
|
||||
set ::env(floorplan_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/floorplan}
|
||||
set ::env(floorplan_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/floorplan}
|
||||
set ::env(floorplan_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/floorplan}
|
||||
set ::env(floorplan_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/floorplan}
|
||||
set ::env(placement_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/placement}
|
||||
set ::env(placement_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/placement}
|
||||
set ::env(placement_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/placement}
|
||||
set ::env(placement_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/placement}
|
||||
set ::env(routing_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing}
|
||||
set ::env(routing_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/routing}
|
||||
set ::env(routing_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing}
|
||||
set ::env(routing_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/routing}
|
||||
set ::env(signoff_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff}
|
||||
set ::env(signoff_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff}
|
||||
set ::env(signoff_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff}
|
||||
set ::env(signoff_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff}
|
||||
set ::env(synthesis_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/synthesis}
|
||||
set ::env(synthesis_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/synthesis}
|
||||
set ::env(synthesis_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/synthesis}
|
||||
set ::env(synthesis_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis}
|
||||
set ::env(SYNTH_MAX_TRAN) {0.75}
|
||||
set ::env(CURRENT_INDEX) 32
|
||||
set ::env(CURRENT_DEF) /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.def
|
||||
set ::env(CURRENT_GUIDE) /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/routing/10-global.guide
|
||||
set ::env(CURRENT_NETLIST) /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.nl.v
|
||||
set ::env(CURRENT_POWERED_NETLIST) {0}
|
||||
set ::env(CURRENT_ODB) /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.odb
|
||||
set ::env(PDK_ROOT) {/home/hosni/swift/OpenLane/pdks}
|
||||
set ::env(ANTENNA_CHECK_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.p.def}
|
||||
set ::env(ANTENNA_VIOLATOR_LIST) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/31-antenna_violators.rpt}
|
||||
set ::env(BASE_SDC_FILE) {/openlane/scripts/base.sdc}
|
||||
set ::env(BASIC_PREP_COMPLETE) {1}
|
||||
set ::env(BOTTOM_MARGIN_MULT) {2}
|
||||
set ::env(CARAVEL_ROOT) {/home/hosni/caravel_sky130/caravel}
|
||||
set ::env(CARRY_SELECT_ADDER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/csa_map.v}
|
||||
set ::env(CELLS_LEF) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELLS_LEF_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_ef_sc_hd.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lef/sky130_fd_sc_hd.lef}
|
||||
set ::env(CELL_CLK_PORT) {CLK}
|
||||
set ::env(CELL_PAD_EXCLUDE) {sky130_fd_sc_hd__tap* sky130_fd_sc_hd__decap* sky130_ef_sc_hd__decap* sky130_fd_sc_hd__fill*}
|
||||
set ::env(CHECK_ASSIGN_STATEMENTS) {0}
|
||||
set ::env(CHECK_UNMAPPED_CELLS) {1}
|
||||
set ::env(CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_4}
|
||||
set ::env(CLK_BUFFER_INPUT) {A}
|
||||
set ::env(CLK_BUFFER_OUTPUT) {X}
|
||||
set ::env(CLOCK_BUFFER_FANOUT) {16}
|
||||
set ::env(CLOCK_PERIOD) {10.0}
|
||||
set ::env(CLOCK_PORT) {}
|
||||
set ::env(CLOCK_TREE_SYNTH) {0}
|
||||
set ::env(CLOCK_WIRE_RC_LAYER) {met5}
|
||||
set ::env(CONFIGS) {general.tcl checkers.tcl synthesis.tcl floorplan.tcl cts.tcl placement.tcl routing.tcl extraction.tcl}
|
||||
set ::env(CORE_AREA) {5.52 5.44 39.1 38.08}
|
||||
set ::env(CORE_HEIGHT) {32.64}
|
||||
set ::env(CORE_WIDTH) {33.58}
|
||||
set ::env(CTS_CLK_BUFFER_LIST) {sky130_fd_sc_hd__clkbuf_8 sky130_fd_sc_hd__clkbuf_4 sky130_fd_sc_hd__clkbuf_2}
|
||||
set ::env(CTS_CLK_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(CTS_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/placement/spare_logic_block.def}
|
||||
set ::env(CTS_DISABLE_POST_PROCESSING) {0}
|
||||
set ::env(CTS_DISTANCE_BETWEEN_BUFFERS) {0}
|
||||
set ::env(CTS_MAX_CAP) {1.53169}
|
||||
set ::env(CTS_REPORT_TIMING) {1}
|
||||
set ::env(CTS_ROOT_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(CTS_SINK_CLUSTERING_MAX_DIAMETER) {50}
|
||||
set ::env(CTS_SINK_CLUSTERING_SIZE) {25}
|
||||
set ::env(CTS_SQR_CAP) {0.258e-3}
|
||||
set ::env(CTS_SQR_RES) {0.125}
|
||||
set ::env(CTS_TARGET_SKEW) {200}
|
||||
set ::env(CTS_TECH_DIR) {N/A}
|
||||
set ::env(CTS_TOLERANCE) {100}
|
||||
set ::env(CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.p.def}
|
||||
set ::env(CURRENT_GDS) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.gds}
|
||||
set ::env(CURRENT_GUIDE) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/routing/10-global.guide}
|
||||
set ::env(CURRENT_INDEX) {32}
|
||||
set ::env(CURRENT_LIB) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/mca/process_corner_nom/spare_logic_block.lib}
|
||||
set ::env(CURRENT_NETLIST) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.nl.v}
|
||||
set ::env(CURRENT_ODB) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.odb}
|
||||
set ::env(CURRENT_POWERED_NETLIST) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.pnl.v}
|
||||
set ::env(CURRENT_SDC) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/floorplan/3-initial_fp.sdc}
|
||||
set ::env(CURRENT_SDF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/mca/process_corner_nom/spare_logic_block.sdf}
|
||||
set ::env(CURRENT_SPEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/mca/process_corner_nom/spare_logic_block.spef}
|
||||
set ::env(CURRENT_STEP) {}
|
||||
set ::env(CVC_SCRIPTS_DIR) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/cvc}
|
||||
set ::env(DATA_WIRE_RC_LAYER) {met2}
|
||||
set ::env(DECAP_CELL) {sky130_ef_sc_hd__decap_12 sky130_fd_sc_hd__decap_8 sky130_fd_sc_hd__decap_6 sky130_fd_sc_hd__decap_4 sky130_fd_sc_hd__decap_3}
|
||||
set ::env(DEFAULT_MAX_TRAN) {0.75}
|
||||
set ::env(DEF_UNITS_PER_MICRON) {1000}
|
||||
set ::env(DESIGN_CONFIG) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/config.tcl}
|
||||
set ::env(DESIGN_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block}
|
||||
set ::env(DESIGN_IS_CORE) {0}
|
||||
set ::env(DESIGN_NAME) {spare_logic_block}
|
||||
set ::env(DETAILED_ROUTER) {tritonroute}
|
||||
set ::env(DIE_AREA) {0.0 0.0 45.0 45.0}
|
||||
set ::env(DIODE_CELL) {sky130_fd_sc_hd__diode_2}
|
||||
set ::env(DIODE_CELL_PIN) {DIODE}
|
||||
set ::env(DIODE_INSERTION_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.def}
|
||||
set ::env(DIODE_INSERTION_STRATEGY) {3}
|
||||
set ::env(DIODE_PADDING) {2}
|
||||
set ::env(DONT_USE_CELLS) {sky130_fd_sc_hd__a2111oi_0 sky130_fd_sc_hd__a21boi_0 sky130_fd_sc_hd__and2_0 sky130_fd_sc_hd__buf_16 sky130_fd_sc_hd__clkdlybuf4s15_1 sky130_fd_sc_hd__clkdlybuf4s18_1 sky130_fd_sc_hd__fa_4 sky130_fd_sc_hd__lpflow_bleeder_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_1 sky130_fd_sc_hd__lpflow_clkbufkapwr_16 sky130_fd_sc_hd__lpflow_clkbufkapwr_2 sky130_fd_sc_hd__lpflow_clkbufkapwr_4 sky130_fd_sc_hd__lpflow_clkbufkapwr_8 sky130_fd_sc_hd__lpflow_clkinvkapwr_1 sky130_fd_sc_hd__lpflow_clkinvkapwr_16 sky130_fd_sc_hd__lpflow_clkinvkapwr_2 sky130_fd_sc_hd__lpflow_clkinvkapwr_4 sky130_fd_sc_hd__lpflow_clkinvkapwr_8 sky130_fd_sc_hd__lpflow_decapkapwr_12 sky130_fd_sc_hd__lpflow_decapkapwr_3 sky130_fd_sc_hd__lpflow_decapkapwr_4 sky130_fd_sc_hd__lpflow_decapkapwr_6 sky130_fd_sc_hd__lpflow_decapkapwr_8 sky130_fd_sc_hd__lpflow_inputiso0n_1 sky130_fd_sc_hd__lpflow_inputiso0p_1 sky130_fd_sc_hd__lpflow_inputiso1n_1 sky130_fd_sc_hd__lpflow_inputiso1p_1 sky130_fd_sc_hd__lpflow_inputisolatch_1 sky130_fd_sc_hd__lpflow_isobufsrc_1 sky130_fd_sc_hd__lpflow_isobufsrc_16 sky130_fd_sc_hd__lpflow_isobufsrc_2 sky130_fd_sc_hd__lpflow_isobufsrc_4 sky130_fd_sc_hd__lpflow_isobufsrc_8 sky130_fd_sc_hd__lpflow_isobufsrckapwr_16 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_1 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_2 sky130_fd_sc_hd__lpflow_lsbuf_lh_hl_isowell_tap_4 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_4 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_1 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_2 sky130_fd_sc_hd__lpflow_lsbuf_lh_isowell_tap_4 sky130_fd_sc_hd__mux4_4 sky130_fd_sc_hd__o21ai_0 sky130_fd_sc_hd__o311ai_0 sky130_fd_sc_hd__or2_0 sky130_fd_sc_hd__probe_p_8 sky130_fd_sc_hd__probec_p_8 sky130_fd_sc_hd__xor3_1 sky130_fd_sc_hd__xor3_2 sky130_fd_sc_hd__xor3_4 sky130_fd_sc_hd__xnor3_1 sky130_fd_sc_hd__xnor3_2 sky130_fd_sc_hd__xnor3_4 }
|
||||
set ::env(DPL_CELL_PADDING) {4}
|
||||
set ::env(DRC_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/26-spare_logic_block.p.def}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
|
||||
set ::env(DRC_EXCLUDE_CELL_LIST_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/drc_exclude.cells}
|
||||
set ::env(DRT_OPT_ITERS) {64}
|
||||
set ::env(ECO_ENABLE) {0}
|
||||
set ::env(ECO_FINISH) {0}
|
||||
set ::env(ECO_ITER) {0}
|
||||
set ::env(ECO_SKIP_PIN) {1}
|
||||
set ::env(EXT_NETLIST) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.spice}
|
||||
set ::env(FAKEDIODE_CELL) {sky130_ef_sc_hd__fakediode_2}
|
||||
set ::env(FILL_CELL) {sky130_fd_sc_hd__fill*}
|
||||
set ::env(FP_ASPECT_RATIO) {1}
|
||||
set ::env(FP_CORE_UTIL) {50}
|
||||
set ::env(FP_ENDCAP_CELL) {sky130_fd_sc_hd__decap_3}
|
||||
set ::env(FP_IO_HEXTEND) {0}
|
||||
set ::env(FP_IO_HLAYER) {met3}
|
||||
set ::env(FP_IO_HLENGTH) {4}
|
||||
set ::env(FP_IO_HTHICKNESS_MULT) {2}
|
||||
set ::env(FP_IO_MIN_DISTANCE) {3}
|
||||
set ::env(FP_IO_MODE) {1}
|
||||
set ::env(FP_IO_UNMATCHED_ERROR) {1}
|
||||
set ::env(FP_IO_VEXTEND) {0}
|
||||
set ::env(FP_IO_VLAYER) {met2}
|
||||
set ::env(FP_IO_VLENGTH) {4}
|
||||
set ::env(FP_IO_VTHICKNESS_MULT) {2}
|
||||
set ::env(FP_PDN_AUTO_ADJUST) {0}
|
||||
set ::env(FP_PDN_CHECK_NODES) {1}
|
||||
set ::env(FP_PDN_CORE_RING) {0}
|
||||
set ::env(FP_PDN_CORE_RING_HOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_CORE_RING_VOFFSET) {6}
|
||||
set ::env(FP_PDN_CORE_RING_VSPACING) {1.7}
|
||||
set ::env(FP_PDN_CORE_RING_VWIDTH) {1.6}
|
||||
set ::env(FP_PDN_ENABLE_GLOBAL_CONNECTIONS) {1}
|
||||
set ::env(FP_PDN_ENABLE_MACROS_GRID) {1}
|
||||
set ::env(FP_PDN_ENABLE_RAILS) {1}
|
||||
set ::env(FP_PDN_HOFFSET) {2}
|
||||
set ::env(FP_PDN_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_PDN_HPITCH) {20}
|
||||
set ::env(FP_PDN_HSPACING) {1.7}
|
||||
set ::env(FP_PDN_HWIDTH) {1.6}
|
||||
set ::env(FP_PDN_IRDROP) {1}
|
||||
set ::env(FP_PDN_LOWER_LAYER) {met4}
|
||||
set ::env(FP_PDN_RAILS_LAYER) {met1}
|
||||
set ::env(FP_PDN_RAIL_OFFSET) {0}
|
||||
set ::env(FP_PDN_RAIL_WIDTH) {0.48}
|
||||
set ::env(FP_PDN_SKIPTRIM) {0}
|
||||
set ::env(FP_PDN_UPPER_LAYER) {met5}
|
||||
set ::env(FP_PDN_VERTICAL_HALO) {10}
|
||||
set ::env(FP_PDN_VOFFSET) {1}
|
||||
set ::env(FP_PDN_VPITCH) {20}
|
||||
set ::env(FP_PDN_VSPACING) {1.7}
|
||||
set ::env(FP_PDN_VWIDTH) {1.6}
|
||||
set ::env(FP_SIZING) {absolute}
|
||||
set ::env(FP_TAPCELL_DIST) {13}
|
||||
set ::env(FP_TAP_HORIZONTAL_HALO) {10}
|
||||
set ::env(FP_TAP_VERTICAL_HALO) {10}
|
||||
set ::env(FP_WELLTAP_CELL) {sky130_fd_sc_hd__tapvpwrvgnd_1}
|
||||
set ::env(FULL_ADDER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/fa_map.v}
|
||||
set ::env(GDS_FILES) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GDS_FILES_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/gds/sky130_fd_sc_hd.gds}
|
||||
set ::env(GENERATE_FINAL_SUMMARY_REPORT) {1}
|
||||
set ::env(GLB_CFG_FILE) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/config.tcl}
|
||||
set ::env(GLB_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(GLB_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(GLB_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_HOLD_SLACK_MARGIN) {0.05}
|
||||
set ::env(GLB_RESIZER_MAX_CAP_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_SLEW_MARGIN) {10}
|
||||
set ::env(GLB_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(GLB_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(GLB_RESIZER_SETUP_SLACK_MARGIN) {0.025}
|
||||
set ::env(GLB_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(GLOBAL_ROUTER) {fastroute}
|
||||
set ::env(GND_NET) {vssd}
|
||||
set ::env(GND_NETS) {vssd}
|
||||
set ::env(GND_PIN) {vssd}
|
||||
set ::env(GPIO_PADS_LEF) { /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_fd_io.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_io/lef/sky130_ef_io.lef }
|
||||
set ::env(GPIO_PADS_LEF_CORE_SIDE) { /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_fd_io_core.lef /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/custom_cells/lef/sky130_ef_io_core.lef }
|
||||
set ::env(GPIO_PADS_PREFIX) {sky130_fd_io sky130_ef_io}
|
||||
set ::env(GPIO_PADS_VERILOG) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/verilog/sky130_fd_io/sky130_ef_io.v}
|
||||
set ::env(GPL_CELL_PADDING) {0}
|
||||
set ::env(GRT_ADJUSTMENT) {0.3}
|
||||
set ::env(GRT_ALLOW_CONGESTION) {0}
|
||||
set ::env(GRT_ANT_ITERS) {3}
|
||||
set ::env(GRT_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(GRT_LAYER_ADJUSTMENTS) {0.99,0,0,0,0,0}
|
||||
set ::env(GRT_MACRO_EXTENSION) {0}
|
||||
set ::env(GRT_MAX_DIODE_INS_ITERS) {1}
|
||||
set ::env(GRT_OVERFLOW_ITERS) {50}
|
||||
set ::env(HOME) {/}
|
||||
set ::env(HOSTNAME) {aa1a570ac10d}
|
||||
set ::env(IO_PCT) {0.2}
|
||||
set ::env(KLAYOUT_DRC_KLAYOUT_GDS) {0}
|
||||
set ::env(KLAYOUT_DRC_TECH_SCRIPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/drc/sky130A_mr.drc}
|
||||
set ::env(KLAYOUT_PROPERTIES) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyp}
|
||||
set ::env(KLAYOUT_TECH) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/klayout/tech/sky130A.lyt}
|
||||
set ::env(KLAYOUT_XOR_GDS) {1}
|
||||
set ::env(KLAYOUT_XOR_THREADS) {1}
|
||||
set ::env(KLAYOUT_XOR_XML) {1}
|
||||
set ::env(LANG) {en_US.UTF-8}
|
||||
set ::env(LAST_TIMING_REPORT_TAG) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/21-rcx_sta}
|
||||
set ::env(LC_ALL) {en_US.UTF-8}
|
||||
set ::env(LC_CTYPE) {en_US.UTF-8}
|
||||
set ::env(LD_LIBRARY_PATH) {/build//lib:/build//lib/Linux-x86_64:}
|
||||
set ::env(LEC_ENABLE) {0}
|
||||
set ::env(LEFT_MARGIN_MULT) {12}
|
||||
set ::env(LIB_CTS) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/cts/cts.lib}
|
||||
set ::env(LIB_FASTEST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ff_n40C_1v95.lib}
|
||||
set ::env(LIB_SLOWEST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SLOWEST_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__ss_100C_1v60.lib}
|
||||
set ::env(LIB_SYNTH) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/trimmed.lib}
|
||||
set ::env(LIB_SYNTH_COMPLETE) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LIB_SYNTH_COMPLETE_NO_PG) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/1-sky130_fd_sc_hd__tt_025C_1v80.no_pg.lib}
|
||||
set ::env(LIB_SYNTH_MERGED) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/merged.lib}
|
||||
set ::env(LIB_SYNTH_NO_PG) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/1-trimmed.no_pg.lib}
|
||||
set ::env(LIB_TYPICAL) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(LOGS_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs}
|
||||
set ::env(LVS_CONNECT_BY_LABEL) {0}
|
||||
set ::env(LVS_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.def}
|
||||
set ::env(LVS_INSERT_POWER_PINS) {1}
|
||||
set ::env(MACRO_BLOCKAGES_LAYER) {li1 met1 met2 met3 met4}
|
||||
set ::env(MAGIC_CONVERT_DRC_TO_RDB) {1}
|
||||
set ::env(MAGIC_DEF_LABELS) {1}
|
||||
set ::env(MAGIC_DEF_NO_BLOCKAGES) {1}
|
||||
set ::env(MAGIC_DISABLE_HIER_GDS) {1}
|
||||
set ::env(MAGIC_DRC_USE_GDS) {1}
|
||||
set ::env(MAGIC_EXT_USE_GDS) {0}
|
||||
set ::env(MAGIC_GDS) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff/spare_logic_block.magic.gds}
|
||||
set ::env(MAGIC_GDS_ALLOW_ABSTRACT) {0}
|
||||
set ::env(MAGIC_GDS_POLYGON_SUBCELLS) {0}
|
||||
set ::env(MAGIC_GENERATE_GDS) {1}
|
||||
set ::env(MAGIC_GENERATE_LEF) {1}
|
||||
set ::env(MAGIC_GENERATE_MAGLEF) {1}
|
||||
set ::env(MAGIC_INCLUDE_GDS_POINTERS) {0}
|
||||
set ::env(MAGIC_MAGICRC) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.magicrc}
|
||||
set ::env(MAGIC_PAD) {0}
|
||||
set ::env(MAGIC_TECH_FILE) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/magic/sky130A.tech}
|
||||
set ::env(MAGIC_WRITE_FULL_LEF) {0}
|
||||
set ::env(MAGIC_ZEROIZE_ORIGIN) {0}
|
||||
set ::env(MAGTYPE) {maglef}
|
||||
set ::env(MANPATH) {/build//share/man:}
|
||||
set ::env(MAX_METAL_LAYER) {6}
|
||||
set ::env(MCW_ROOT) {/home/hosni/caravel_sky130/caravel_mgmt_soc_litex}
|
||||
set ::env(MC_SDF_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/mca/sdf}
|
||||
set ::env(MC_SPEF_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/mca/spef}
|
||||
set ::env(MERGED_LEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.nom.lef}
|
||||
set ::env(MERGED_LEF_MAX) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.max.lef}
|
||||
set ::env(MERGED_LEF_MIN) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/merged.min.lef}
|
||||
set ::env(MISMATCHES_OK) {1}
|
||||
set ::env(NETGEN_SETUP_FILE) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/netgen/sky130A_setup.tcl}
|
||||
set ::env(NO_SYNTH_CELL_LIST) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/no_synth.cells}
|
||||
set ::env(OPENLANE_ROOT) {/openlane}
|
||||
set ::env(OPENLANE_RUN_TAG) {23_02_27_06_20}
|
||||
set ::env(OPENLANE_VERBOSE) {1}
|
||||
set ::env(OPENLANE_VERSION) {1ed36219093ce86ddbc1b981e461c5f38e5bba72}
|
||||
set ::env(OPENROAD) {/build/}
|
||||
set ::env(OPENROAD_BIN) {openroad}
|
||||
set ::env(PARSITICS_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/spare_logic_block.def}
|
||||
set ::env(PATH) {/openlane:/openlane/scripts:/build//bin:/build//bin/Linux-x86_64:/build//pdn/scripts:/usr/local/sbin:/usr/local/bin:/usr/sbin:/usr/bin:/sbin:/bin}
|
||||
set ::env(PDK) {sky130A}
|
||||
set ::env(PDKPATH) {/home/hosni/swift/OpenLane/pdks/sky130A}
|
||||
set ::env(PDK_ROOT) {/home/hosni/swift/OpenLane/pdks}
|
||||
set ::env(PDN_CFG) {/openlane/scripts/openroad/common/pdn_cfg.tcl}
|
||||
set ::env(PLACEMENT_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/floorplan/6-pdn.def}
|
||||
set ::env(PLACE_SITE) {unithd}
|
||||
set ::env(PLACE_SITE_HEIGHT) {2.720}
|
||||
set ::env(PLACE_SITE_WIDTH) {0.460}
|
||||
set ::env(PL_BASIC_PLACEMENT) {0}
|
||||
set ::env(PL_ESTIMATE_PARASITICS) {1}
|
||||
set ::env(PL_INIT_COEFF) {0.00002}
|
||||
set ::env(PL_IO_ITER) {5}
|
||||
set ::env(PL_LIB) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/lib/sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(PL_MACRO_CHANNEL) {0 0}
|
||||
set ::env(PL_MACRO_HALO) {0 0}
|
||||
set ::env(PL_MAX_DISPLACEMENT_X) {500}
|
||||
set ::env(PL_MAX_DISPLACEMENT_Y) {100}
|
||||
set ::env(PL_OPTIMIZE_MIRRORING) {1}
|
||||
set ::env(PL_RANDOM_GLB_PLACEMENT) {0}
|
||||
set ::env(PL_RANDOM_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_RESIZER_ALLOW_SETUP_VIOS) {0}
|
||||
set ::env(PL_RESIZER_BUFFER_INPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_BUFFER_OUTPUT_PORTS) {1}
|
||||
set ::env(PL_RESIZER_DESIGN_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_RESIZER_HOLD_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_HOLD_SLACK_MARGIN) {0.1}
|
||||
set ::env(PL_RESIZER_MAX_CAP_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_SLEW_MARGIN) {20}
|
||||
set ::env(PL_RESIZER_MAX_WIRE_LENGTH) {0}
|
||||
set ::env(PL_RESIZER_REPAIR_TIE_FANOUT) {1}
|
||||
set ::env(PL_RESIZER_SETUP_MAX_BUFFER_PERCENT) {50}
|
||||
set ::env(PL_RESIZER_SETUP_SLACK_MARGIN) {0.05}
|
||||
set ::env(PL_RESIZER_TIE_SEPERATION) {0}
|
||||
set ::env(PL_RESIZER_TIMING_OPTIMIZATIONS) {0}
|
||||
set ::env(PL_ROUTABILITY_DRIVEN) {1}
|
||||
set ::env(PL_SKIP_INITIAL_PLACEMENT) {0}
|
||||
set ::env(PL_TARGET_DENSITY) {0.45}
|
||||
set ::env(PL_TIME_DRIVEN) {1}
|
||||
set ::env(PRIMARY_SIGNOFF_TOOL) {magic}
|
||||
set ::env(PROCESS) {130}
|
||||
set ::env(PWD) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane}
|
||||
set ::env(QUIT_ON_HOLD_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_ILLEGAL_OVERLAPS) {1}
|
||||
set ::env(QUIT_ON_LONG_WIRE) {0}
|
||||
set ::env(QUIT_ON_LVS_ERROR) {1}
|
||||
set ::env(QUIT_ON_MAGIC_DRC) {1}
|
||||
set ::env(QUIT_ON_SETUP_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TIMING_VIOLATIONS) {1}
|
||||
set ::env(QUIT_ON_TR_DRC) {1}
|
||||
set ::env(QUIT_ON_XOR_ERROR) {0}
|
||||
set ::env(RCX_CC_MODEL) {10}
|
||||
set ::env(RCX_CONTEXT_DEPTH) {5}
|
||||
set ::env(RCX_CORNER_COUNT) {1}
|
||||
set ::env(RCX_COUPLING_THRESHOLD) {0.1}
|
||||
set ::env(RCX_MAX_RESISTANCE) {50}
|
||||
set ::env(RCX_MERGE_VIA_WIRE_RES) {1}
|
||||
set ::env(RCX_RULES) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.nom.calibre}
|
||||
set ::env(RCX_RULES_MAX) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.max.calibre}
|
||||
set ::env(RCX_RULES_MIN) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/rules.openrcx.sky130A.min.calibre}
|
||||
set ::env(RCX_SDC_FILE) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/floorplan/3-initial_fp.sdc}
|
||||
set ::env(REPORTS_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports}
|
||||
set ::env(RESULTS_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results}
|
||||
set ::env(RE_BUFFER_CELL) {sky130_fd_sc_hd__buf_4}
|
||||
set ::env(RIGHT_MARGIN_MULT) {12}
|
||||
set ::env(RIPPLE_CARRY_ADDER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/rca_map.v}
|
||||
set ::env(ROOT_CLK_BUFFER) {sky130_fd_sc_hd__clkbuf_16}
|
||||
set ::env(ROUTING_CORES) {2}
|
||||
set ::env(ROUTING_CURRENT_DEF) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/placement/spare_logic_block.def}
|
||||
set ::env(RSZ_DONT_TOUCH_RX) {\$^}
|
||||
set ::env(RSZ_LIB) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis/resizer_sky130_fd_sc_hd__tt_025C_1v80.lib}
|
||||
set ::env(RSZ_USE_OLD_REMOVER) {0}
|
||||
set ::env(RT_MAX_LAYER) {met5}
|
||||
set ::env(RT_MIN_LAYER) {met1}
|
||||
set ::env(RUN_CVC) {1}
|
||||
set ::env(RUN_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20}
|
||||
set ::env(RUN_DRT) {1}
|
||||
set ::env(RUN_FILL_INSERTION) {1}
|
||||
set ::env(RUN_IRDROP_REPORT) {1}
|
||||
set ::env(RUN_KLAYOUT) {1}
|
||||
set ::env(RUN_KLAYOUT_DRC) {0}
|
||||
set ::env(RUN_KLAYOUT_XOR) {1}
|
||||
set ::env(RUN_LVS) {1}
|
||||
set ::env(RUN_MAGIC) {1}
|
||||
set ::env(RUN_MAGIC_DRC) {1}
|
||||
set ::env(RUN_SPEF_EXTRACTION) {1}
|
||||
set ::env(RUN_STANDALONE) {1}
|
||||
set ::env(RUN_TAG) {23_02_27_06_20}
|
||||
set ::env(RUN_TAP_DECAP_INSERTION) {1}
|
||||
set ::env(SCLPATH) {/home/hosni/swift/OpenLane/pdks/sky130A/sky130_fd_sc_hd}
|
||||
set ::env(SCRIPTS_DIR) {/openlane/scripts}
|
||||
set ::env(SHLVL) {1}
|
||||
set ::env(SPEF_EXTRACTOR) {openrcx}
|
||||
set ::env(START_TIME) {2023.02.27_14.20.21}
|
||||
set ::env(STA_PRE_CTS) {0}
|
||||
set ::env(STA_REPORT_POWER) {1}
|
||||
set ::env(STA_WRITE_LIB) {1}
|
||||
set ::env(STD_CELL_GROUND_PINS) {VGND VNB}
|
||||
set ::env(STD_CELL_LIBRARY) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_CDL) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_LIBRARY_OPT) {sky130_fd_sc_hd}
|
||||
set ::env(STD_CELL_LIBRARY_OPT_CDL) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/cdl/sky130_fd_sc_hd.cdl}
|
||||
set ::env(STD_CELL_POWER_PINS) {VPWR VPB}
|
||||
set ::env(SYNTH_ADDER_TYPE) {YOSYS}
|
||||
set ::env(SYNTH_BIN) {yosys}
|
||||
set ::env(SYNTH_BUFFERING) {1}
|
||||
set ::env(SYNTH_CAP_LOAD) {33.442}
|
||||
set ::env(SYNTH_CLOCK_TRANSITION) {0.15}
|
||||
set ::env(SYNTH_CLOCK_UNCERTAINTY) {0.25}
|
||||
set ::env(SYNTH_DRIVING_CELL) {sky130_fd_sc_hd__inv_2}
|
||||
set ::env(SYNTH_DRIVING_CELL_PIN) {Y}
|
||||
set ::env(SYNTH_ELABORATE_ONLY) {0}
|
||||
set ::env(SYNTH_EXTRA_MAPPING_FILE) {}
|
||||
set ::env(SYNTH_FLAT_TOP) {0}
|
||||
set ::env(SYNTH_LATCH_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/latch_map.v}
|
||||
set ::env(SYNTH_MAX_FANOUT) {10}
|
||||
set ::env(SYNTH_MAX_TRAN) {0.75}
|
||||
set ::env(SYNTH_MIN_BUF_PORT) {sky130_fd_sc_hd__buf_2 A X}
|
||||
set ::env(SYNTH_MUX4_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux4_map.v}
|
||||
set ::env(SYNTH_MUX_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/mux2_map.v}
|
||||
set ::env(SYNTH_NO_FLAT) {0}
|
||||
set ::env(SYNTH_OPT) {0}
|
||||
set ::env(SYNTH_READ_BLACKBOX_LIB) {1}
|
||||
set ::env(SYNTH_SCRIPT) {/openlane/scripts/yosys/synth.tcl}
|
||||
set ::env(SYNTH_SHARE_RESOURCES) {1}
|
||||
set ::env(SYNTH_SIZING) {0}
|
||||
set ::env(SYNTH_STRATEGY) {AREA 0}
|
||||
set ::env(SYNTH_TIEHI_PORT) {sky130_fd_sc_hd__conb_1 HI}
|
||||
set ::env(SYNTH_TIELO_PORT) {sky130_fd_sc_hd__conb_1 LO}
|
||||
set ::env(SYNTH_TIMING_DERATE) {0.05}
|
||||
set ::env(TAKE_LAYOUT_SCROT) {0}
|
||||
set ::env(TECH_LEF) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TECH_LEF_MAX) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__max.tlef}
|
||||
set ::env(TECH_LEF_MIN) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__min.tlef}
|
||||
set ::env(TECH_LEF_OPT) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.ref/sky130_fd_sc_hd/techlef/sky130_fd_sc_hd__nom.tlef}
|
||||
set ::env(TECH_METAL_LAYERS) {li1 met1 met2 met3 met4 met5}
|
||||
set ::env(TERM) {xterm}
|
||||
set ::env(TERMINAL_OUTPUT) {/dev/null}
|
||||
set ::env(TMP_DIR) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp}
|
||||
set ::env(TOP_MARGIN_MULT) {2}
|
||||
set ::env(TRACKS_INFO_FILE) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tracks.info}
|
||||
set ::env(TRACKS_INFO_FILE_PROCESSED) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/routing/config.tracks}
|
||||
set ::env(TRISTATE_BUFFER_MAP) {/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/sky130_fd_sc_hd/tribuff_map.v}
|
||||
set ::env(USE_ARC_ANTENNA_CHECK) {1}
|
||||
set ::env(USE_GPIO_PADS) {0}
|
||||
set ::env(VCHECK_OUTPUT) {}
|
||||
set ::env(VDD_NET) {vccd}
|
||||
set ::env(VDD_NETS) {vccd}
|
||||
set ::env(VDD_PIN) {vccd}
|
||||
set ::env(VERILOG_FILES) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/../../verilog/rtl/spare_logic_block.v}
|
||||
set ::env(VERILOG_FILES_BLACKBOX) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/../../verilog/stubs/sky130_fd_sc_hd__tapvpwrvgnd_1.v}
|
||||
set ::env(WIRE_RC_LAYER) {met1}
|
||||
set ::env(YOSYS_REWRITE_VERILOG) {0}
|
||||
set ::env(_) {/openlane/flow.tcl}
|
||||
set ::env(cts_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/cts}
|
||||
set ::env(cts_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/cts}
|
||||
set ::env(cts_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/cts}
|
||||
set ::env(cts_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/cts}
|
||||
set ::env(drc_prefix) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc}
|
||||
set ::env(eco_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/eco}
|
||||
set ::env(eco_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/eco}
|
||||
set ::env(eco_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/eco}
|
||||
set ::env(eco_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/eco}
|
||||
set ::env(floorplan_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/floorplan}
|
||||
set ::env(floorplan_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/floorplan}
|
||||
set ::env(floorplan_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/floorplan}
|
||||
set ::env(floorplan_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/floorplan}
|
||||
set ::env(fp_report_prefix) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/floorplan/3-initial_fp}
|
||||
set ::env(placement_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/placement}
|
||||
set ::env(placement_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/placement}
|
||||
set ::env(placement_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/placement}
|
||||
set ::env(placement_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/placement}
|
||||
set ::env(routing_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/routing}
|
||||
set ::env(routing_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/routing}
|
||||
set ::env(routing_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing}
|
||||
set ::env(routing_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/routing}
|
||||
set ::env(signoff_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff}
|
||||
set ::env(signoff_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff}
|
||||
set ::env(signoff_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/signoff}
|
||||
set ::env(signoff_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff}
|
||||
set ::env(synth_report_prefix) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/synthesis/1-synthesis}
|
||||
set ::env(synthesis_logs) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/synthesis}
|
||||
set ::env(synthesis_reports) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/synthesis}
|
||||
set ::env(synthesis_results) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/synthesis}
|
||||
set ::env(synthesis_tmpfiles) {/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/synthesis}
|
||||
set ::env(timer_end) {1677507647}
|
||||
set ::env(timer_routed) {1677507633}
|
||||
set ::env(timer_start) {1677507621}
|
||||
|
|
@ -1,2 +0,0 @@
|
|||
,design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,suggested_clock_frequency,suggested_clock_period,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GLB_RT_ADJUSTMENT,STD_CELL_LIBRARY,CELL_PAD,DIODE_INSERTION_STRATEGY
|
||||
0,/home/ma/ef/caravel_openframe/openlane/spare_logic_block,spare_logic_block,spare_logic_block,flow_completed,0h0m57s,-1,39506.17283950618,0.002025,19753.08641975309,24.3,466.03,40,0,-1,-1,-1,-1,0,0,-1,0,0,-1,1021,172,0.0,0.0,-1,0.0,-1,0.0,0.0,-1,0.0,-1,977964.0,12.24,11.05,8.12,0.0,0.0,0.0,10,96,10,96,0,0,0,40,0,0,0,0,0,0,0,4,-1,-1,-1,24,14,0,38,90.9090909090909,11.0,10.0,AREA 0,5,50,1,20,20,0.45,0.0,sky130_fd_sc_hd,4,3
|
||||
|
|
|
@ -0,0 +1,16 @@
|
|||
Design Name: spare_logic_block
|
||||
Run Directory: /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20
|
||||
----------------------------------------
|
||||
|
||||
Magic DRC Summary:
|
||||
Source: /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/drc.rpt
|
||||
Total Magic DRC violations is 0
|
||||
----------------------------------------
|
||||
|
||||
LVS Summary:
|
||||
Source: /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/logs/signoff/spare_logic_block.lvs.lef.log
|
||||
Source not found.
|
||||
----------------------------------------
|
||||
|
||||
Antenna Summary:
|
||||
No antenna report found.
|
||||
|
|
@ -0,0 +1,2 @@
|
|||
design,design_name,config,flow_status,total_runtime,routed_runtime,(Cell/mm^2)/Core_Util,DIEAREA_mm^2,CellPer_mm^2,OpenDP_Util,Peak_Memory_Usage_MB,cell_count,tritonRoute_violations,Short_violations,MetSpc_violations,OffGrid_violations,MinHole_violations,Other_violations,Magic_violations,antenna_violations,lvs_total_errors,cvc_total_errors,klayout_violations,wire_length,vias,wns,pl_wns,optimized_wns,fastroute_wns,spef_wns,tns,pl_tns,optimized_tns,fastroute_tns,spef_tns,HPWL,routing_layer1_pct,routing_layer2_pct,routing_layer3_pct,routing_layer4_pct,routing_layer5_pct,routing_layer6_pct,wires_count,wire_bits,public_wires_count,public_wire_bits,memories_count,memory_bits,processes_count,cells_pre_abc,AND,DFF,NAND,NOR,OR,XOR,XNOR,MUX,inputs,outputs,level,EndCaps,TapCells,Diodes,Total_Physical_Cells,CoreArea_um^2,power_slowest_internal_uW,power_slowest_switching_uW,power_slowest_leakage_uW,power_typical_internal_uW,power_typical_switching_uW,power_typical_leakage_uW,power_fastest_internal_uW,power_fastest_switching_uW,power_fastest_leakage_uW,critical_path_ns,suggested_clock_period,suggested_clock_frequency,CLOCK_PERIOD,SYNTH_STRATEGY,SYNTH_MAX_FANOUT,FP_CORE_UTIL,FP_ASPECT_RATIO,FP_PDN_VPITCH,FP_PDN_HPITCH,PL_TARGET_DENSITY,GRT_ADJUSTMENT,STD_CELL_LIBRARY,DIODE_INSERTION_STRATEGY
|
||||
/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block,spare_logic_block,23_02_27_06_20,flow completed,0h0m26s0ms,0h0m12s0ms,39506.17283950617,0.002025,19753.086419753086,24.3,486.01,40,0,0,0,0,0,0,0,0,0,-1,-1,979,168,0.0,0.0,-1,0.0,0.0,0.0,0.0,-1,0.0,0.0,1043540.0,0.0,12.56,15.21,0.0,0.0,0.0,10,96,10,96,0,0,0,40,0,0,0,0,0,0,0,0,-1,-1,-1,24,14,0,38,1096.0511999999999,-1,-1,-1,-1,-1,-1,-1,-1,-1,-1,10.0,100.0,10.0,3,1,50,20,20,0.3,0.45,sky130_fd_sc_hd,10,AREA 0
|
||||
|
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_design_area
|
||||
============================================================================
|
||||
Design area 258 u^2 24% utilization.
|
||||
|
|
@ -0,0 +1 @@
|
|||
SKIPPED!
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -path_delay max (Setup)
|
||||
============================================================================
|
||||
No paths found.
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -path_delay min (Hold)
|
||||
============================================================================
|
||||
No paths found.
|
||||
|
|
@ -0,0 +1,100 @@
|
|||
|
||||
===========================================================================
|
||||
report_parasitic_annotation -report_unannotated
|
||||
============================================================================
|
||||
Found 27 unannotated nets.
|
||||
spare_logic1\[0\]
|
||||
spare_logic1\[10\]
|
||||
spare_logic1\[11\]
|
||||
spare_logic1\[12\]
|
||||
spare_logic1\[13\]
|
||||
spare_logic1\[14\]
|
||||
spare_logic1\[15\]
|
||||
spare_logic1\[16\]
|
||||
spare_logic1\[17\]
|
||||
spare_logic1\[18\]
|
||||
spare_logic1\[19\]
|
||||
spare_logic1\[1\]
|
||||
spare_logic1\[20\]
|
||||
spare_logic1\[21\]
|
||||
spare_logic1\[22\]
|
||||
spare_logic1\[23\]
|
||||
spare_logic1\[24\]
|
||||
spare_logic1\[25\]
|
||||
spare_logic1\[26\]
|
||||
spare_logic1\[2\]
|
||||
spare_logic1\[3\]
|
||||
spare_logic1\[4\]
|
||||
spare_logic1\[5\]
|
||||
spare_logic1\[6\]
|
||||
spare_logic1\[7\]
|
||||
spare_logic1\[8\]
|
||||
spare_logic1\[9\]
|
||||
Found 0 partially unannotated nets.
|
||||
parastic_annotation_check
|
||||
check_slew
|
||||
|
||||
===========================================================================
|
||||
report_check_types -max_slew -max_cap -max_fanout -violators
|
||||
============================================================================
|
||||
|
||||
===========================================================================
|
||||
max slew violation count 0
|
||||
max fanout violation count 0
|
||||
max cap violation count 0
|
||||
============================================================================
|
||||
check_slew_end
|
||||
tns_report
|
||||
|
||||
===========================================================================
|
||||
report_tns
|
||||
============================================================================
|
||||
tns 0.00
|
||||
tns_report_end
|
||||
wns_report
|
||||
|
||||
===========================================================================
|
||||
report_wns
|
||||
============================================================================
|
||||
wns 0.00
|
||||
wns_report_end
|
||||
worst_slack
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -max (Setup)
|
||||
============================================================================
|
||||
worst slack INF
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -min (Hold)
|
||||
============================================================================
|
||||
worst slack INF
|
||||
worst_slack_end
|
||||
power_report
|
||||
|
||||
===========================================================================
|
||||
report_power
|
||||
============================================================================
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.23e-14 2.16e-14 2.71e-11 2.71e-11 7.1%
|
||||
Combinational 0.00e+00 0.00e+00 3.54e-10 3.54e-10 92.9%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.23e-14 2.16e-14 3.81e-10 3.81e-10 100.0%
|
||||
0.0% 0.0% 100.0%
|
||||
power_report_end
|
||||
area_report
|
||||
|
||||
===========================================================================
|
||||
report_design_area
|
||||
============================================================================
|
||||
Design area 258 u^2 24% utilization.
|
||||
area_report_end
|
||||
Setting global connections for newly added cells...
|
||||
[WARNING] Did not save OpenROAD database!
|
||||
Writing SDF to /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/mca/process_corner_nom/spare_logic_block.sdf...
|
||||
Writing timing model to /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/results/routing/mca/process_corner_nom/spare_logic_block.lib...
|
||||
|
||||
|
|
@ -0,0 +1,14 @@
|
|||
|
||||
===========================================================================
|
||||
report_power
|
||||
============================================================================
|
||||
Group Internal Switching Leakage Total
|
||||
Power Power Power Power (Watts)
|
||||
----------------------------------------------------------------
|
||||
Sequential 1.23e-14 2.16e-14 2.71e-11 2.71e-11 7.1%
|
||||
Combinational 0.00e+00 0.00e+00 3.54e-10 3.54e-10 92.9%
|
||||
Macro 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
Pad 0.00e+00 0.00e+00 0.00e+00 0.00e+00 0.0%
|
||||
----------------------------------------------------------------
|
||||
Total 1.23e-14 2.16e-14 3.81e-10 3.81e-10 100.0%
|
||||
0.0% 0.0% 100.0%
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
===========================================================================
|
||||
report_checks -unconstrained
|
||||
============================================================================
|
||||
No paths found.
|
||||
|
||||
===========================================================================
|
||||
report_checks --slack_max -0.01
|
||||
============================================================================
|
||||
No paths found.
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
===========================================================================
|
||||
report_check_types -max_slew -max_cap -max_fanout -violators
|
||||
============================================================================
|
||||
|
||||
===========================================================================
|
||||
max slew violation count 0
|
||||
max fanout violation count 0
|
||||
max cap violation count 0
|
||||
============================================================================
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_tns
|
||||
============================================================================
|
||||
tns 0.00
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
|
||||
===========================================================================
|
||||
report_wns
|
||||
============================================================================
|
||||
wns 0.00
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
|
||||
===========================================================================
|
||||
report_worst_slack -max (Setup)
|
||||
============================================================================
|
||||
worst slack INF
|
||||
|
||||
===========================================================================
|
||||
report_worst_slack -min (Hold)
|
||||
============================================================================
|
||||
worst slack INF
|
||||
|
|
@ -0,0 +1,112 @@
|
|||
Instance name, X location, Y location, Voltage
|
||||
FILLER_11_53, 26.52, 35.36, 1.8
|
||||
FILLER_11_57, 26.52, 35.36, 1.8
|
||||
FILLER_10_46, 26.52, 29.92, 1.8
|
||||
FILLER_10_53, 26.52, 29.92, 1.8
|
||||
spare_logic_const\[11\], 26.52, 29.92, 1.8
|
||||
spare_logic_const\[2\], 26.52, 29.92, 1.8
|
||||
spare_logic_const\[3\], 26.52, 29.92, 1.8
|
||||
spare_logic_nand\[0\], 26.52, 29.92, 1.8
|
||||
FILLER_7_57, 26.52, 24.48, 1.8
|
||||
FILLER_8_46, 26.52, 24.48, 1.8
|
||||
spare_logic_mux\[0\], 26.52, 24.48, 1.8
|
||||
FILLER_5_40, 26.52, 19.04, 1.8
|
||||
FILLER_5_48, 26.52, 19.04, 1.8
|
||||
FILLER_5_57, 26.52, 19.04, 1.8
|
||||
spare_logic_nor\[0\], 26.52, 19.04, 1.8
|
||||
FILLER_2_41, 26.52, 13.6, 1.8
|
||||
FILLER_3_43, 26.52, 13.6, 1.8
|
||||
FILLER_3_52, 26.52, 13.6, 1.8
|
||||
spare_logic_const\[25\], 26.52, 13.6, 1.8
|
||||
spare_logic_nand\[1\], 26.52, 13.6, 1.8
|
||||
FILLER_0_46, 26.52, 8.16, 1.8
|
||||
FILLER_0_57, 26.52, 8.16, 1.8
|
||||
FILLER_1_36, 26.52, 8.16, 1.8
|
||||
FILLER_1_44, 26.52, 8.16, 1.8
|
||||
FILLER_1_51, 26.52, 8.16, 1.8
|
||||
FILLER_1_57, 26.52, 8.16, 1.8
|
||||
spare_logic_const\[21\], 26.52, 8.16, 1.8
|
||||
spare_logic_const\[6\], 26.52, 8.16, 1.8
|
||||
spare_logic_inv\[0\], 26.52, 8.16, 1.8
|
||||
FILLER_11_3, 6.52, 35.36, 1.8
|
||||
spare_logic_const\[4\], 6.52, 35.36, 1.8
|
||||
FILLER_9_12, 6.52, 29.92, 1.8
|
||||
FILLER_9_3, 6.52, 29.92, 1.8
|
||||
spare_logic_biginv, 6.52, 29.92, 1.8
|
||||
spare_logic_nor\[1\], 6.52, 29.92, 1.8
|
||||
FILLER_8_8, 6.52, 24.48, 1.8
|
||||
spare_logic_const\[12\], 6.52, 24.48, 1.8
|
||||
spare_logic_const\[18\], 6.52, 24.48, 1.8
|
||||
FILLER_5_3, 6.52, 19.04, 1.8
|
||||
FILLER_6_3, 6.52, 19.04, 1.8
|
||||
spare_logic_const\[7\], 6.52, 19.04, 1.8
|
||||
spare_logic_mux\[1\], 6.52, 19.04, 1.8
|
||||
FILLER_3_13, 6.52, 13.6, 1.8
|
||||
FILLER_3_3, 6.52, 13.6, 1.8
|
||||
spare_logic_const\[0\], 6.52, 13.6, 1.8
|
||||
FILLER_0_8, 6.52, 8.16, 1.8
|
||||
FILLER_1_3, 6.52, 8.16, 1.8
|
||||
FILLER_2_8, 6.52, 8.16, 1.8
|
||||
spare_logic_const\[16\], 6.52, 8.16, 1.8
|
||||
spare_logic_const\[19\], 6.52, 8.16, 1.8
|
||||
spare_logic_const\[22\], 6.52, 8.16, 1.8
|
||||
spare_logic_flop\[1\], 6.52, 8.16, 1.8
|
||||
PHY_20, 5.52, 35.36, 1.8
|
||||
PHY_22, 5.52, 35.36, 1.8
|
||||
FILLER_10_61, 39.1, 35.36, 1.8
|
||||
PHY_21, 39.1, 35.36, 1.8
|
||||
PHY_23, 39.1, 35.36, 1.8
|
||||
spare_logic_const\[13\], 39.1, 35.36, 1.8
|
||||
spare_logic_inv\[2\], 39.1, 35.36, 1.8
|
||||
FILLER_10_14, 16.52, 35.36, 1.8
|
||||
spare_logic_inv\[3\], 16.52, 35.36, 1.8
|
||||
PHY_16, 5.52, 29.92, 1.8
|
||||
PHY_18, 5.52, 29.92, 1.8
|
||||
FILLER_8_60, 39.1, 29.92, 1.8
|
||||
FILLER_9_62, 39.1, 29.92, 1.8
|
||||
PHY_17, 39.1, 29.92, 1.8
|
||||
PHY_19, 39.1, 29.92, 1.8
|
||||
FILLER_8_20, 16.52, 29.92, 1.8
|
||||
FILLER_9_19, 16.52, 29.92, 1.8
|
||||
FILLER_9_27, 16.52, 29.92, 1.8
|
||||
spare_logic_const\[10\], 16.52, 29.92, 1.8
|
||||
spare_logic_const\[14\], 16.52, 29.92, 1.8
|
||||
spare_logic_const\[5\], 16.52, 29.92, 1.8
|
||||
spare_logic_const\[8\], 16.52, 29.92, 1.8
|
||||
PHY_12, 5.52, 24.48, 1.8
|
||||
PHY_14, 5.52, 24.48, 1.8
|
||||
FILLER_6_65, 39.1, 24.48, 1.8
|
||||
PHY_13, 39.1, 24.48, 1.8
|
||||
PHY_15, 39.1, 24.48, 1.8
|
||||
spare_logic_const\[17\], 39.1, 24.48, 1.8
|
||||
FILLER_6_19, 16.52, 24.48, 1.8
|
||||
spare_logic_const\[20\], 16.52, 24.48, 1.8
|
||||
PHY_10, 5.52, 19.04, 1.8
|
||||
PHY_8, 5.52, 19.04, 1.8
|
||||
FILLER_4_65, 39.1, 19.04, 1.8
|
||||
FILLER_5_64, 39.1, 19.04, 1.8
|
||||
PHY_11, 39.1, 19.04, 1.8
|
||||
PHY_9, 39.1, 19.04, 1.8
|
||||
spare_logic_const\[9\], 39.1, 19.04, 1.8
|
||||
PHY_4, 5.52, 13.6, 1.8
|
||||
PHY_6, 5.52, 13.6, 1.8
|
||||
FILLER_2_62, 39.1, 13.6, 1.8
|
||||
FILLER_3_62, 39.1, 13.6, 1.8
|
||||
PHY_5, 39.1, 13.6, 1.8
|
||||
PHY_7, 39.1, 13.6, 1.8
|
||||
FILLER_2_15, 16.52, 13.6, 1.8
|
||||
FILLER_2_22, 16.52, 13.6, 1.8
|
||||
spare_logic_const\[15\], 16.52, 13.6, 1.8
|
||||
spare_logic_flop\[0\], 16.52, 13.6, 1.8
|
||||
PHY_0, 5.52, 8.16, 1.8
|
||||
PHY_2, 5.52, 8.16, 1.8
|
||||
PHY_1, 39.1, 8.16, 1.8
|
||||
PHY_3, 39.1, 8.16, 1.8
|
||||
spare_logic_const\[1\], 39.1, 8.16, 1.8
|
||||
spare_logic_inv\[1\], 39.1, 8.16, 1.8
|
||||
FILLER_0_17, 16.52, 8.16, 1.8
|
||||
FILLER_0_24, 16.52, 8.16, 1.8
|
||||
spare_logic_const\[23\], 16.52, 8.16, 1.8
|
||||
spare_logic_const\[24\], 16.52, 8.16, 1.8
|
||||
spare_logic_const\[26\], 16.52, 8.16, 1.8
|
||||
|
||||
|
|
@ -0,0 +1 @@
|
|||
Total XOR differences = 2322
|
||||
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,3 @@
|
|||
LVS reports no net, device, pin, or property mismatches.
|
||||
|
||||
Total errors = 0
|
||||
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" ?>
|
||||
<report-database>
|
||||
<categories/>
|
||||
<cells>
|
||||
<cell>
|
||||
<name>spare_logic_block</name>
|
||||
</cell>
|
||||
</cells>
|
||||
<items/>
|
||||
</report-database>
|
||||
|
|
@ -0,0 +1 @@
|
|||
$spare_logic_block 100
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
spare_logic_block
|
||||
----------------------------------------
|
||||
[INFO]: COUNT: 0
|
||||
[INFO]: Should be divided by 3 or 4
|
||||
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:37 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.002:0.002:0.002))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.002:0.002:0.002))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:37 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.002:0.002:0.002))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.002:0.002:0.002))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:37 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.002:0.002:0.002))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.002:0.002:0.002))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:35 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:35 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:35 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:40 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -0,0 +1,243 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Mon Feb 27 14:20:40 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
(INSTANCE)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(INTERCONNECT spare_logic_biginv.Y spare_xib (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_xz[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[0\].LO spare_logic_inv\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_xz[10] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[10\].LO spare_logic_nor\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_xz[11] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[11\].LO spare_logic_nor\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_xz[12] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[12\].LO spare_logic_nor\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_xz[13] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[13\].LO spare_logic_mux\[0\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_xz[14] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[14\].LO spare_logic_mux\[1\].A0 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_xz[15] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[15\].LO spare_logic_mux\[0\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_xz[16] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[16\].LO spare_logic_mux\[1\].A1 (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_xz[17] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[17\].LO spare_logic_mux\[0\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_xz[18] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[18\].LO spare_logic_mux\[1\].S (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_xz[19] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[19\].LO spare_logic_flop\[0\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_xz[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[1\].LO spare_logic_inv\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_xz[20] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[20\].LO spare_logic_flop\[1\].D (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_xz[21] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[21\].LO spare_logic_flop\[0\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_xz[22] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[22\].LO spare_logic_flop\[1\].CLK (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_xz[23] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[23\].LO spare_logic_flop\[0\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_xz[24] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[24\].LO spare_logic_flop\[1\].SET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_xz[25] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[25\].LO spare_logic_flop\[0\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_xz[26] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[26\].LO spare_logic_flop\[1\].RESET_B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_xz[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[2\].LO spare_logic_inv\[2\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_xz[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[3\].LO spare_logic_inv\[3\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_xz[4] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[4\].LO spare_logic_biginv.A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_xz[5] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[5\].LO spare_logic_nand\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_xz[6] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[6\].LO spare_logic_nand\[1\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_xz[7] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[7\].LO spare_logic_nand\[0\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_xz[8] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[8\].LO spare_logic_nand\[1\].B (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_xz[9] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_const\[9\].LO spare_logic_nor\[0\].A (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q spare_xfq[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[0\].Q_N spare_xfqn[0] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q spare_xfq[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_flop\[1\].Q_N spare_xfqn[1] (0.001:0.001:0.001))
|
||||
(INTERCONNECT spare_logic_inv\[0\].Y spare_xi[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[1\].Y spare_xi[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[2\].Y spare_xi[2] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_inv\[3\].Y spare_xi[3] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[0\].X spare_xmx[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_mux\[1\].X spare_xmx[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[0\].Y spare_xna[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nand\[1\].Y spare_xna[1] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[0\].Y spare_xno[0] (0.000:0.000:0.000))
|
||||
(INTERCONNECT spare_logic_nor\[1\].Y spare_xno[1] (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_8")
|
||||
(INSTANCE spare_logic_biginv)
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__dfbbp_1")
|
||||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
(REMOVAL (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge SET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(REMOVAL (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(RECOVERY (posedge RESET_B) (posedge CLK) (0.000:0.000:0.000))
|
||||
(HOLD D (posedge CLK) (0.000:0.000:0.000))
|
||||
(SETUP D (posedge CLK) (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[2\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__inv_2")
|
||||
(INSTANCE spare_logic_inv\[3\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__mux2_2")
|
||||
(INSTANCE spare_logic_mux\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A0 X (0.000:0.000:0.000))
|
||||
(IOPATH A1 X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
(IOPATH S X (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nand2_2")
|
||||
(INSTANCE spare_logic_nand\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
(CELL
|
||||
(CELLTYPE "sky130_fd_sc_hd__nor2_2")
|
||||
(INSTANCE spare_logic_nor\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH A Y (0.000:0.000:0.000))
|
||||
(IOPATH B Y (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
)
|
||||
)
|
||||
|
|
@ -1,14 +1,14 @@
|
|||
(DELAYFILE
|
||||
(SDFVERSION "3.0")
|
||||
(DESIGN "spare_logic_block")
|
||||
(DATE "Tue Dec 14 12:28:12 2021")
|
||||
(DATE "Mon Feb 27 14:20:40 2023")
|
||||
(VENDOR "Parallax")
|
||||
(PROGRAM "STA")
|
||||
(VERSION "2.3.1")
|
||||
(VERSION "2.3.2")
|
||||
(DIVIDER .)
|
||||
(VOLTAGE 1.800:1.800:1.800)
|
||||
(PROCESS "1.000:1.000:1.000")
|
||||
(TEMPERATURE 25.000:25.000:25.000)
|
||||
(VOLTAGE 1.600::1.600)
|
||||
(PROCESS "1.000::1.000")
|
||||
(TEMPERATURE 100.000::100.000)
|
||||
(TIMESCALE 1ns)
|
||||
(CELL
|
||||
(CELLTYPE "spare_logic_block")
|
||||
|
|
@ -101,12 +101,12 @@
|
|||
(INSTANCE spare_logic_flop\[0\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
|
|
@ -123,12 +123,12 @@
|
|||
(INSTANCE spare_logic_flop\[1\])
|
||||
(DELAY
|
||||
(ABSOLUTE
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q_N (0.000:0.000:0.000))
|
||||
(IOPATH RESET_B Q () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q_N () (0.000:0.000:0.000))
|
||||
(IOPATH SET_B Q (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q_N (0.000:0.000:0.000))
|
||||
(IOPATH CLK Q (0.000:0.000:0.000))
|
||||
)
|
||||
)
|
||||
(TIMINGCHECK
|
||||
|
|
|
|||
|
|
@ -0,0 +1,51 @@
|
|||
CVC: Log output to /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/spare_logic_block.rpt
|
||||
CVC: Error output to /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/spare_logic_block.rpt.error.gz
|
||||
CVC: Debug output to /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/spare_logic_block.rpt.debug.gz
|
||||
CVC: Circuit Validation Check Version 1.1.4
|
||||
CVC: Start: Mon Feb 27 14:20:47 2023
|
||||
|
||||
Using the following parameters for CVC (Circuit Validation Check) from /home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/cvc/cvcrc
|
||||
CVC_TOP = 'spare_logic_block'
|
||||
CVC_NETLIST = '/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/spare_logic_block.cdl'
|
||||
CVC_MODE = 'spare_logic_block'
|
||||
CVC_MODEL_FILE = '/home/hosni/swift/OpenLane/pdks/sky130A/libs.tech/openlane/cvc/models'
|
||||
CVC_POWER_FILE = '/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/spare_logic_block.power'
|
||||
CVC_FUSE_FILE = ''
|
||||
CVC_REPORT_FILE = '/home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/reports/signoff/spare_logic_block.rpt'
|
||||
CVC_REPORT_TITLE = 'CVC $CVC_TOP'
|
||||
CVC_CIRCUIT_ERROR_LIMIT = '100'
|
||||
CVC_SEARCH_LIMIT = '100'
|
||||
CVC_LEAK_LIMIT = '0.0002'
|
||||
CVC_SOI = 'false'
|
||||
CVC_SCRC = 'false'
|
||||
CVC_VTH_GATES = 'false'
|
||||
CVC_MIN_VTH_GATES = 'false'
|
||||
CVC_IGNORE_VTH_FLOATING = 'false'
|
||||
CVC_IGNORE_NO_LEAK_FLOATING = 'false'
|
||||
CVC_LEAK_OVERVOLTAGE = 'true'
|
||||
CVC_LOGIC_DIODES = 'false'
|
||||
CVC_ANALOG_GATES = 'true'
|
||||
CVC_BACKUP_RESULTS = 'false'
|
||||
CVC_MOS_DIODE_ERROR_THRESHOLD = '0'
|
||||
CVC_SHORT_ERROR_THRESHOLD = '0'
|
||||
CVC_BIAS_ERROR_THRESHOLD = '0'
|
||||
CVC_FORWARD_ERROR_THRESHOLD = '0'
|
||||
CVC_FLOATING_ERROR_THRESHOLD = '0'
|
||||
CVC_GATE_ERROR_THRESHOLD = '0'
|
||||
CVC_LEAK?_ERROR_THRESHOLD = '0'
|
||||
CVC_EXPECTED_ERROR_THRESHOLD = '0'
|
||||
CVC_OVERVOLTAGE_ERROR_THRESHOLD = '0'
|
||||
CVC_PARALLEL_CIRCUIT_PORT_LIMIT = '0'
|
||||
CVC_CELL_ERROR_LIMIT_FILE = ''
|
||||
CVC_CELL_CHECKSUM_FILE = ''
|
||||
CVC_LARGE_CIRCUIT_SIZE = '10000000'
|
||||
CVC_NET_CHECK_FILE = ''
|
||||
CVC_MODEL_CHECK_FILE = ''
|
||||
End of parameters
|
||||
|
||||
CVC: Reading device model settings...
|
||||
CVC: Reading power settings...
|
||||
CVC: Parsing netlist /home/hosni/caravel_sky130/caravel_redesign-2/caravel/openlane/spare_logic_block/runs/23_02_27_06_20/tmp/signoff/spare_logic_block.cdl
|
||||
Cdl fixed data size 20106
|
||||
Usage CDL: Time: 0 Memory: 6736 I/O: 8 Swap: 0
|
||||
CVC: Counting and linking...
|
||||
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
File diff suppressed because it is too large
Load Diff
|
|
@ -0,0 +1,440 @@
|
|||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6043 2703 6101 2737
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6135 2703 6193 2737
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6227 2703 6256 2737
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
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|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
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|
||||
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||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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||||
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
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||||
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5123 3791 5181 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5215 3791 5273 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5307 3791 5365 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5399 3791 5457 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5491 3791 5520 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5599 3791 5641 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5675 3791 5733 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5767 3791 5825 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5859 3791 5917 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5951 3791 6009 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6009 3791 6043 3825
|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
box 6043 3791 6101 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6135 3791 6193 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 7055 3791 7084 3825
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 2605 4335 2639 4369
|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 1869 4879 1903 4913
|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
box 1903 5423 1961 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 2823 4335 2852 4369
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 2915 4879 2973 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 2973 4879 3007 4913
|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3467 4879 3525 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 2852 4335 2881 4369
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3467 4335 3525 4369
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3588 4335 3617 4369
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3651 4335 3680 4369
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3680 4879 3709 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3743 4879 3772 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3680 4335 3709 4369
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3709 4335 3743 4369
|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
box 3743 4335 3772 4369
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 2944 5423 2973 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 2973 5423 3007 5457
|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
box 3007 5423 3065 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3191 5423 3249 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3283 5423 3341 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 3559 5423 3617 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
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|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6348 4879 6377 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6411 4879 6469 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6503 4879 6561 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6595 4879 6653 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6687 4879 6745 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6779 4879 6837 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6871 4879 6929 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6963 4879 7001 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6256 4879 6285 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6319 4879 6348 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5599 5423 5641 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5859 5423 5917 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6043 5423 6101 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6227 5423 6256 5457
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6999 4879 7021 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 7055 4879 7084 4913
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 4232 5967 4261 6001
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 4261 5967 4295 6001
|
||||
feedback add "Illegal overlap between obsli1c and locali (types do not connect)" medium
|
||||
box 4295 5967 4324 6001
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 4324 5967 4353 6001
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 4387 5967 4445 6001
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 4508 5967 4537 6001
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 4571 5967 4629 6001
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 4663 5967 4721 6001
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
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|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5336 6511 5365 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5399 6511 5457 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5491 6511 5549 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5583 6511 5601 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5599 6511 5641 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5675 6511 5704 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5980 6511 6009 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 6043 6511 6072 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5704 6511 5733 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5767 6511 5825 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5859 6511 5917 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
box 5951 6511 5980 6545
|
||||
feedback add "Illegal overlap between obsli1 and locali (types do not connect)" medium
|
||||
File diff suppressed because one or more lines are too long
|
|
@ -0,0 +1,106 @@
|
|||
- status: 0 - openlane design prep
|
||||
runtime_s: 1.79
|
||||
runtime_ts: 0h0m1s790ms
|
||||
- status: 1 - synthesis - yosys
|
||||
runtime_s: 1.24
|
||||
runtime_ts: 0h0m1s241ms
|
||||
- status: 2 - sta - openroad
|
||||
runtime_s: 0.43
|
||||
runtime_ts: 0h0m0s428ms
|
||||
- status: 3 - floorplan initialization - openroad
|
||||
runtime_s: 0.55
|
||||
runtime_ts: 0h0m0s552ms
|
||||
- status: 4 - ioplace - openroad
|
||||
runtime_s: 0.42
|
||||
runtime_ts: 0h0m0s422ms
|
||||
- status: 5 - tap/decap insertion - openroad
|
||||
runtime_s: 0.44
|
||||
runtime_ts: 0h0m0s444ms
|
||||
- status: 6 - pdn generation - openroad
|
||||
runtime_s: 0.46
|
||||
runtime_ts: 0h0m0s457ms
|
||||
- status: 7 - global placement - openroad
|
||||
runtime_s: 0.57
|
||||
runtime_ts: 0h0m0s570ms
|
||||
- status: 8 - detailed placement - openroad
|
||||
runtime_s: 0.47
|
||||
runtime_ts: 0h0m0s470ms
|
||||
- status: 9 - detailed placement - openroad
|
||||
runtime_s: 0.47
|
||||
runtime_ts: 0h0m0s472ms
|
||||
- status: 11 - write verilog - openroad
|
||||
runtime_s: 0.42
|
||||
runtime_ts: 0h0m0s418ms
|
||||
- status: 11 - global routing - openroad
|
||||
runtime_s: 0.52
|
||||
runtime_ts: 0h0m0s517ms
|
||||
- status: 12 - fill insertion - openroad
|
||||
runtime_s: 0.48
|
||||
runtime_ts: 0h0m0s483ms
|
||||
- status: 13 - detailed_routing - openroad
|
||||
runtime_s: 1.81
|
||||
runtime_ts: 0h0m1s806ms
|
||||
- status: 14 - wire lengths - openlane
|
||||
runtime_s: 0.26
|
||||
runtime_ts: 0h0m0s262ms
|
||||
- status: 15 - parasitics extraction - openroad
|
||||
runtime_s: 0.46
|
||||
runtime_ts: 0h0m0s462ms
|
||||
- status: 16 - sta - openroad
|
||||
runtime_s: 1.54
|
||||
runtime_ts: 0h0m1s542ms
|
||||
- status: 17 - parasitics extraction - openroad
|
||||
runtime_s: 0.45
|
||||
runtime_ts: 0h0m0s454ms
|
||||
- status: 18 - sta - openroad
|
||||
runtime_s: 1.55
|
||||
runtime_ts: 0h0m1s551ms
|
||||
- status: 19 - parasitics extraction - openroad
|
||||
runtime_s: 0.45
|
||||
runtime_ts: 0h0m0s447ms
|
||||
- status: 20 - sta - openroad
|
||||
runtime_s: 1.54
|
||||
runtime_ts: 0h0m1s536ms
|
||||
- status: 21 - sta - openroad
|
||||
runtime_s: 0.39
|
||||
runtime_ts: 0h0m0s392ms
|
||||
- status: 22 - ir drop report - openroad
|
||||
runtime_s: 0.42
|
||||
runtime_ts: 0h0m0s424ms
|
||||
- status: 23 - gdsii - magic
|
||||
runtime_s: 1.38
|
||||
runtime_ts: 0h0m1s383ms
|
||||
- status: 24 - gdsii - klayout
|
||||
runtime_s: 0.44
|
||||
runtime_ts: 0h0m0s438ms
|
||||
- status: 25 - xor - klayout
|
||||
runtime_s: 0.41
|
||||
runtime_ts: 0h0m0s415ms
|
||||
- status: 26 - spice extraction - magic
|
||||
runtime_s: 0.44
|
||||
runtime_ts: 0h0m0s441ms
|
||||
- status: 28 - write verilog - openroad
|
||||
runtime_s: 0.4
|
||||
runtime_ts: 0h0m0s403ms
|
||||
- status: 28 - write powered verilog - openlane
|
||||
runtime_s: 0.52
|
||||
runtime_ts: 0h0m0s517ms
|
||||
- status: 29 - lvs - netgen
|
||||
runtime_s: 0.1
|
||||
runtime_ts: 0h0m0s102ms
|
||||
- status: 30 - drc - magic
|
||||
runtime_s: 1.18
|
||||
runtime_ts: 0h0m1s175ms
|
||||
- status: 31 - antenna check - openroad
|
||||
runtime_s: 0.46
|
||||
runtime_ts: 0h0m0s458ms
|
||||
- status: 32 - erc - circuit validity checker
|
||||
runtime_s: 0.13
|
||||
runtime_ts: 0h0m0s133ms
|
||||
---
|
||||
- status: routed
|
||||
runtime_s: 12.0
|
||||
runtime_ts: 0h0m12s0ms
|
||||
- status: flow completed
|
||||
runtime_s: 26.0
|
||||
runtime_ts: 0h0m26s0ms
|
||||
|
|
@ -4,36 +4,36 @@
|
|||
.subckt sky130_fd_sc_hd__decap_4 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__conb_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__conb_1 VGND VNB VPB VPWR HI LO
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_12 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_12 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_8 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_8 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__nor2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__nor2_2 A B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_ef_sc_hd__decap_12 abstract view
|
||||
.subckt sky130_ef_sc_hd__decap_12 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_1 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_1 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__fill_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__fill_2 VGND VNB VPB VPWR
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__nor2_2 abstract view
|
||||
.subckt sky130_fd_sc_hd__nor2_2 A B VGND VNB VPB VPWR Y
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_6 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_6 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__decap_3 abstract view
|
||||
.subckt sky130_fd_sc_hd__decap_3 VGND VNB VPB VPWR
|
||||
.ends
|
||||
|
||||
* Black-box entry subcircuit for sky130_fd_sc_hd__dfbbp_1 abstract view
|
||||
|
|
@ -68,49 +68,50 @@
|
|||
+ spare_xz[26] spare_xz[2] spare_xz[3] spare_xz[4] spare_xz[5] spare_xz[6] spare_xz[7]
|
||||
+ spare_xz[8] spare_xz[9] vccd vssd
|
||||
XFILLER_0_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_0_46 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_0_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_0_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xspare_logic_const\[8\] vssd vssd vccd vccd spare_logic_const\[8\]/HI spare_xz[8]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_3_35 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_3_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_0_47 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_3_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_3_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_7_8 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_9_23 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_9_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_nor\[0\] spare_xz[9] spare_xz[11] vssd vssd vccd vccd spare_xno[0] sky130_fd_sc_hd__nor2_2
|
||||
Xspare_logic_const\[22\] vssd vssd vccd vccd spare_logic_const\[22\]/HI spare_xz[22]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_3_47 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_9_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_24 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_0_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_9_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_9_35 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_3_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_6_25 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xspare_logic_const\[15\] vssd vssd vccd vccd spare_logic_const\[15\]/HI spare_xz[15]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_9_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_6_59 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_11_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_11_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
Xspare_logic_const\[6\] vssd vssd vccd vccd spare_logic_const\[6\]/HI spare_xz[6]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_48 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_0_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_6_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xspare_logic_const\[20\] vssd vssd vccd vccd spare_logic_const\[20\]/HI spare_xz[20]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_1_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_9_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_1_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_0_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_6_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_0 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[13\] vssd vssd vccd vccd spare_logic_const\[13\]/HI spare_xz[13]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_4_61 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_1_62 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_7_61 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_6_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_1_51 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_1_40 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_6_29 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XPHY_1 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[4\] vssd vssd vccd vccd spare_logic_const\[4\]/HI spare_xz[4]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_7_51 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_61 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_6_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_2 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_4_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_3_9 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_4_41 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_9_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_flop\[0\] spare_xz[21] spare_xz[19] spare_xz[25] spare_xz[23] vssd vssd
|
||||
+ vccd vccd spare_xfq[0] spare_xfqn[0] sky130_fd_sc_hd__dfbbp_1
|
||||
XPHY_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
|
|
@ -118,97 +119,96 @@ Xspare_logic_mux\[1\] spare_xz[14] spare_xz[16] spare_xz[18] vssd vssd vccd vccd
|
|||
+ sky130_fd_sc_hd__mux2_2
|
||||
Xspare_logic_const\[11\] vssd vssd vccd vccd spare_logic_const\[11\]/HI spare_xz[11]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_4_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_4_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_4_53 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_7_20 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XPHY_4 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_4_65 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_const\[2\] vssd vssd vccd vccd spare_logic_const\[2\]/HI spare_xz[2]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_1_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_1_44 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_1_44 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_1_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_7_32 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XPHY_5 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_inv\[3\] spare_xz[3] vssd vssd vccd vccd spare_xi[3] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_10_21 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_7_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_1_9 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_7_44 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XPHY_6 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_8_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_10_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_22 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_1_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_1_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_7 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_4_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_10_34 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_1_36 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_const\[0\] vssd vssd vccd vccd spare_logic_const\[0\]/HI spare_xz[0]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_7_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_7_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_7_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_inv\[1\] spare_xz[1] vssd vssd vccd vccd spare_xi[1] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_4_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_46 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_1_48 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_7_69 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_10_57 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_46 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[25\] vssd vssd vccd vccd spare_logic_const\[25\]/HI spare_xz[25]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_1_38 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_4_15 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_6_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
Xspare_logic_nand\[1\] spare_xz[6] spare_xz[8] vssd vssd vccd vccd spare_xna[1] sky130_fd_sc_hd__nand2_2
|
||||
XFILLER_6_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_7_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_10_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
Xspare_logic_const\[18\] vssd vssd vccd vccd spare_logic_const\[18\]/HI spare_xz[18]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_10_59 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_7_27 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_4_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_10_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xspare_logic_const\[9\] vssd vssd vccd vccd spare_logic_const\[9\]/HI spare_xz[9]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_8_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_10_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_8_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
Xspare_logic_nor\[1\] spare_xz[10] spare_xz[12] vssd vssd vccd vccd spare_xno[1] sky130_fd_sc_hd__nor2_2
|
||||
XFILLER_7_39 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_2_50 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_8_60 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
Xspare_logic_const\[23\] vssd vssd vccd vccd spare_logic_const\[23\]/HI spare_xz[23]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_4_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_4_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_4_29 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_4_3 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XTAP_30 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_62 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_2_62 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_8_50 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
Xspare_logic_const\[16\] vssd vssd vccd vccd spare_logic_const\[16\]/HI spare_xz[16]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_5_40 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_10_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XTAP_31 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XTAP_32 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
Xspare_logic_const\[7\] vssd vssd vccd vccd spare_logic_const\[7\]/HI spare_xz[7]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_5_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_biginv spare_xz[4] vssd vssd vccd vccd spare_xib sky130_fd_sc_hd__inv_8
|
||||
XFILLER_8_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
Xspare_logic_const\[21\] vssd vssd vccd vccd spare_logic_const\[21\]/HI spare_xz[21]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_5_31 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_5_64 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_6_9 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XTAP_33 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_2_54 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_11_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_11_41 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_2_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_8_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_8_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XTAP_34 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_43 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
Xspare_logic_const\[14\] vssd vssd vccd vccd spare_logic_const\[14\]/HI spare_xz[14]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_11_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_2_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_10_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_5_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_35 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_11 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xspare_logic_const\[5\] vssd vssd vccd vccd spare_logic_const\[5\]/HI spare_xz[5]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XTAP_35 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_24 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_4_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_8_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_36 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XTAP_25 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_11_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_20 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_0_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_8_34 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_0_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xspare_logic_flop\[1\] spare_xz[22] spare_xz[20] spare_xz[26] spare_xz[24] vssd vssd
|
||||
+ vccd vccd spare_xfq[1] spare_xfqn[1] sky130_fd_sc_hd__dfbbp_1
|
||||
XFILLER_5_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
|
|
@ -218,62 +218,67 @@ Xspare_logic_const\[12\] vssd vssd vccd vccd spare_logic_const\[12\]/HI spare_xz
|
|||
+ sky130_fd_sc_hd__conb_1
|
||||
XTAP_26 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XPHY_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_2_47 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_8_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_8_46 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_27 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_11_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_11_57 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_22 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_const\[3\] vssd vssd vccd vccd spare_logic_const\[3\]/HI spare_xz[3]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_2_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XPHY_11 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_11_68 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_2_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XTAP_28 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_5_48 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_12 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XPHY_23 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_11_14 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_5_16 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_9_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_mux\[0\] spare_xz[13] spare_xz[15] spare_xz[17] vssd vssd vccd vccd spare_xmx[0]
|
||||
+ sky130_fd_sc_hd__mux2_2
|
||||
XPHY_13 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XTAP_29 vssd vccd sky130_fd_sc_hd__tapvpwrvgnd_1
|
||||
XFILLER_11_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_11_26 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xspare_logic_const\[10\] vssd vssd vccd vccd spare_logic_const\[10\]/HI spare_xz[10]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_11_27 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_2_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_8_16 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_5_28 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XFILLER_2_29 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XPHY_14 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_0_8 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
Xspare_logic_const\[1\] vssd vssd vccd vccd spare_logic_const\[1\]/HI spare_xz[1]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XPHY_15 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
Xspare_logic_inv\[2\] spare_xz[2] vssd vssd vccd vccd spare_xi[2] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_8_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_3_62 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_8_29 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
Xspare_logic_const\[26\] vssd vssd vccd vccd spare_logic_const\[26\]/HI spare_xz[26]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_5_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_11_29 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_11_29 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XPHY_16 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_7_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_0_42 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_7_3 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_3_52 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_9_62 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XPHY_17 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_41 vssd vssd vccd vccd sky130_fd_sc_hd__decap_12
|
||||
XFILLER_6_41 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
Xspare_logic_const\[19\] vssd vssd vccd vccd spare_logic_const\[19\]/HI spare_xz[19]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_9_63 vssd vssd vccd vccd sky130_fd_sc_hd__decap_6
|
||||
XFILLER_0_54 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XPHY_18 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_53 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_6_53 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
Xspare_logic_inv\[0\] spare_xz[0] vssd vssd vccd vccd spare_xi[0] sky130_fd_sc_hd__inv_2
|
||||
XFILLER_9_20 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_0_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_0_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_3_43 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_9_42 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
XPHY_19 vssd vssd vccd vccd sky130_fd_sc_hd__decap_3
|
||||
XFILLER_9_9 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_6_65 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_const\[24\] vssd vssd vccd vccd spare_logic_const\[24\]/HI spare_xz[24]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
XFILLER_6_10 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
Xspare_logic_nand\[0\] spare_xz[5] spare_xz[7] vssd vssd vccd vccd spare_xna[0] sky130_fd_sc_hd__nand2_2
|
||||
XFILLER_3_55 vssd vssd vccd vccd sky130_fd_sc_hd__fill_1
|
||||
XFILLER_3_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_0_34 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_6_66 vssd vssd vccd vccd sky130_fd_sc_hd__decap_4
|
||||
XFILLER_5_3 vssd vssd vccd vccd sky130_fd_sc_hd__decap_8
|
||||
XFILLER_9_54 vssd vssd vccd vccd sky130_fd_sc_hd__fill_2
|
||||
XFILLER_0_34 vssd vssd vccd vccd sky130_ef_sc_hd__decap_12
|
||||
Xspare_logic_const\[17\] vssd vssd vccd vccd spare_logic_const\[17\]/HI spare_xz[17]
|
||||
+ sky130_fd_sc_hd__conb_1
|
||||
.ends
|
||||
|
|
|
|||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue