- high level changes:
* add larger buffers on output ports
* add buffers on input ports
* adjust sdc file increasing output load and setting a high transition
- detailed changes:
* add interactive script for openlane where the order of events is a bit shuffled
- to add obstruction before pdn
- to manually insert buffers on some ports
- to manually remove buffers inserted by synthesis on for example serial_clock_out
* change openlane config adding extra row and columns to increase the space and fit the
added buffers
* change config to enable buffering
* increase density for better placement?
* change the cell exclude list. some excluded cells didn't make sense
* ef decap cells break dynamic sims?
* add custom pdn script for to duplicate the old pdn
- misc changes:
* fix openlane makefile to properly detect interactive script
!important still need to run dynamic simulations
!important depends on some updates to openlane
update gpio_control_block config for new openlane versions:
- disable `SYNTH_BUFFERING` and `SYNTH_SIZING` to limit the design size
and fit the floorplan
- change `SYNTH_STRATEGY` to `AREA 0` to minimize design cells
- disable `PL_RESIZER_TIMING_OPTIMIZATIONS` and
enable `GLB_RESIZER_TIMING_OPTIMIZATIONS`
- remove `FP_IO_*` and replace them with `FP_DEF_TEMPLATE` for io placement
- set `DECAP_CELL` to not use ef decaps.. i think that was for simulations?
- enable some turned off `QUIT_*` variables
- replace deprecated variables such as `GLB_RT_*`
- customize `pdn.tcl` to force pdn straps to follow the old pattern
- replace `$script_dir` with `$::env(DESIGN_DIR)`
!IMPORTANT - still need to run dynamic simulations
* - update caravan configuration
* change correct gpio_default blocks instance names
* implement powerrouting work around
* place spare logic blocks
* keep the history of runs and sym link last/final one
* - update caravan mag, def and gl views
- add fake power routing cell in the rtl as a placeholder for openlane
to prevent routing on that cell
- fix some syntax errors in chip_io_alt
- match simple_por lef pins with mag by regenerating it
* Apply automatic changes to Manifest and README.rst
* add caravan power routing lef
* - update mag and def view of caravan
- add_macro_placement for fake cell
* Added back the power routing to Caravan, fixed DRC errors, ran LVS,
corrected placement of isolated substrate regions, and replaced the
signal routing for the analog lines. Be aware that merging with
main may cause issues with the mgmt_protect.mag file and its
subcells mprj2_logic_high.mag and mprj_logic_high.mag. It may be
worth cherry-picking the files to merge and exclude those layouts.
Co-authored-by: kareem <kareem.farid@efabless.com>
Co-authored-by: kareefardi <kareefardi@users.noreply.github.com>
Co-authored-by: Jeff DiCorpo <42048757+jeffdi@users.noreply.github.com>
* REVERT ME: temporarily match simple_por pin in verilog with lef
* - update configs
- add patch file for power routing def
* - update the following caravel toplevel views
- gl
- mag
- def
- add caravel power routing def
* Apply automatic changes to Manifest and README.rst
* update gl mag and def for caravel
* Revert "REVERT ME: temporarily match simple_por pin in verilog with lef"
This reverts commit b70c27c69f.
* update caravel gds
* Apply automatic changes to Manifest and README.rst
* Added text and logo cells back into the caravel top level. Put an
isolated ground marker layer on the xres_buf layout. Corrected
the power supply pin names on the gate level verilog netlist of
simple_por in caravel.v. Updated the copyright block text.
Corrected DRC errors in the top level routing.
Co-authored-by: Tim Edwards <tim@opencircuitdesign.com>
* - add openlane patch file to for input buffering workaround
- update configuration of mgmt protect
* mgmt_protect updated
* mgmt_protect updated
* remove some via3 to fix power shorts
Co-authored-by: Marwan Abbas <marwan@ciic.c.catx-ext-efabless.internal>
kareem
Anton Blanchard
Kareem Farid
R. Timothy Edwards
manarabdelaty