M0stafaRady
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71829abbc5
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Merge branch 'cocotb' of github.com:efabless/caravel into cocotb
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2022-10-11 14:00:58 -07:00 |
M0stafaRady
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2a5c7b876b
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fix some timeout and errors due to cpu became slower and sram interface are deleted
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2022-10-11 14:00:49 -07:00 |
M0stafaRady
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de6d55f3ee
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trial for increase SPI clock
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2022-10-11 13:44:56 -07:00 |
M0stafaRady
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bd40646465
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Update caravel to force high at gpio3 at the start of test
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2022-10-11 08:30:02 -07:00 |
M0stafaRady
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9cc8ebf28a
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update verify_cocotb script to include sdf
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2022-10-11 07:30:37 -07:00 |
M0stafaRady
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3fe7f3f38b
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fix tests timeout
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2022-10-11 06:04:16 -07:00 |
M0stafaRady
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7fe790649d
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Add gpio_all_bidir_user test
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2022-10-10 15:59:20 -07:00 |
M0stafaRady
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8cca3a5002
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Add gpio_all_i_pd_user and gpio_all_i_pu_user
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2022-10-10 14:49:24 -07:00 |
M0stafaRady
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a572a8ec14
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add gpio_all_i_user test
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2022-10-10 09:07:32 -07:00 |
M0stafaRady
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e2245ad333
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enhance gpio_all_i test to include more checkers
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2022-10-10 07:42:02 -07:00 |
M0stafaRady
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71d53b9958
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added netlist for vcs gl_caravel_vcs.list rtl_caravel_vcs.list
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2022-10-10 06:23:47 -07:00 |
M0stafaRady
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688429eeda
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move caravel.py, cpu.py ... to interfaces directory
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2022-10-10 04:50:45 -07:00 |
M0stafaRady
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45a885caaa
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update verify_cocotb script to be dependent on CARAVEL_ROOT and MCW_ROOT
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2022-10-10 04:34:26 -07:00 |
M0stafaRady
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00364eb092
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Add gpio_all_o_user test
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2022-10-09 07:53:25 -07:00 |
M0stafaRady
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1690c8e068
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enhance gpio_all_o test
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2022-10-09 06:07:19 -07:00 |
M0stafaRady
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08229d6a9b
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Add gpio_all_bidir test but it still not working yet
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2022-10-09 05:08:12 -07:00 |
M0stafaRady
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e94a8e0477
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add test la test
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2022-10-08 06:25:26 -07:00 |
M0stafaRady
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d90001eac2
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update caravel.py to disable bin 3 also
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2022-10-08 01:56:41 -07:00 |
M0stafaRady
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2dc29bb207
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comment disabling the housekeeping at the begining of each test as it's not needed anymore
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2022-10-07 07:02:58 -07:00 |
M0stafaRady
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0f167fc041
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update timeout for gpio_all_i_pd and gpio_all_i_pu
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2022-10-07 07:02:09 -07:00 |
M0stafaRady
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f072e9cb2d
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Add gpio_all_i_pd
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2022-10-07 06:41:21 -07:00 |
M0stafaRady
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e1eba1d534
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update gpio_all_i_pu test
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2022-10-07 06:04:18 -07:00 |
M0stafaRady
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3eb0b11380
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update verify_cocotb.py to remove vcs generate files
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2022-10-06 11:18:48 -07:00 |
M0stafaRady
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4f483adb36
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update hk_regs_wr_wb_cpu test to include all house keeping regs
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2022-10-06 11:16:07 -07:00 |
M0stafaRady
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7e407e1155
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Add test hk_disable
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2022-10-06 10:12:12 -07:00 |
M0stafaRady
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28b453783f
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Add clock redirect test
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2022-10-06 09:20:06 -07:00 |
M0stafaRady
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fb34d9a541
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update input tests to cover the gpio from 32 to 37
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2022-10-06 05:32:46 -07:00 |
M0stafaRady
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a69185dfca
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update verify_cocotb.py script to collect coverage only when -cov is passed
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2022-10-06 04:44:55 -07:00 |
M0stafaRady
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1bc78c4eea
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update verify_cocotb.py script to collect coverage only when -cov is passed
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2022-10-06 04:43:02 -07:00 |
M0stafaRady
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8e72d5e13e
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Add test uart_loopback
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2022-10-06 03:12:44 -07:00 |
M0stafaRady
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6830c79ae8
|
fix uart_rx tests by sending in reverse and use uart_ev_pending_write(UART_EV_RX);
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2022-10-06 02:14:59 -07:00 |
M0stafaRady
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a6e7b46128
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delete reading from uart register in uart_rx test
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2022-10-05 15:07:38 -07:00 |
M0stafaRady
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78613c95cc
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increase timeout for uart_rx and add uart_ev_pending_write
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2022-10-05 15:02:07 -07:00 |
M0stafaRady
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8e21a2f722
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Add test pll
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2022-10-05 13:58:36 -07:00 |
M0stafaRady
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b31efbdeea
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IO[0] affects the uart selecting btw system and debug
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2022-10-05 13:47:23 -07:00 |
M0stafaRady
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fca511f306
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change docker mount from the home to repo directory and pdk root
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2022-10-05 11:10:24 -07:00 |
M0stafaRady
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4610f6b004
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Add trial of test gpio_all_i_pu still not work
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2022-10-05 08:22:51 -07:00 |
M0stafaRady
|
e2b345dcbb
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Add new test user_pass_thru_rd
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2022-10-04 10:55:53 -07:00 |
M0stafaRady
|
0bd6c73b7b
|
update verify_cocotb script to merge coverage
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2022-10-04 10:47:07 -07:00 |
M0stafaRady
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5e523bce5b
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Add spi master temp created to simulate the silicon validation test and to be removed after
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2022-10-04 10:46:34 -07:00 |
M0stafaRady
|
11330823b7
|
Add hk_regs_wr_wb_cpu test
|
2022-10-04 03:24:15 -07:00 |
M0stafaRady
|
ef9c2e408b
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fix bug at IRQ_uart
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2022-10-03 09:49:51 -07:00 |
M0stafaRady
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37244a2514
|
add 3 regressions r_rtl , r_gl,r_sdf
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2022-10-03 09:01:08 -07:00 |
M0stafaRady
|
e81416bb51
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add new test mgmt_gpio_bidir
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2022-10-03 08:56:46 -07:00 |
M0stafaRady
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e945c3b882
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fix bug at mgmt_gpio_out by increasing the number of phases
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2022-10-03 05:45:55 -07:00 |
M0stafaRady
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79f26f6b38
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add new test spi_master_rd
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2022-10-03 05:36:36 -07:00 |
M0stafaRady
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55f6f56921
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update verify_cocotb script to run iverilog inside a docker
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2022-10-03 01:56:08 -07:00 |
M0stafaRady
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de2f4a3707
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Add bitbang_spi_i test
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2022-10-02 08:38:00 -07:00 |
M0stafaRady
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9812aedaa1
|
Update README.md
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2022-10-02 15:50:18 +02:00 |
M0stafaRady
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f0494ef4b1
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update make file to take user_project_wrapper file as input for iverilog
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2022-10-02 06:48:29 -07:00 |
M0stafaRady
|
927c216a6b
|
Merge branch 'cocotb' of github.com:efabless/caravel into cocotb
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2022-10-02 06:38:32 -07:00 |
M0stafaRady
|
752d12928b
|
fix iverlog command for the new structure
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2022-10-02 06:38:22 -07:00 |
M0stafaRady
|
d8a4b812e8
|
update script to make hex_files directory if not exists and to take argument -vcs if it will work in vcs mode
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2022-10-02 06:37:12 -07:00 |
M0stafaRady
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00a029fec3
|
Update README.md
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2022-10-02 15:17:21 +02:00 |
M0stafaRady
|
bf9b363f68
|
Update README.md
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2022-10-02 15:01:15 +02:00 |
M0stafaRady
|
32607cc118
|
delete uart_rx hex
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2022-10-02 05:40:44 -07:00 |
M0stafaRady
|
b045977af0
|
merge with remote branch
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2022-10-02 05:39:23 -07:00 |
M0stafaRady
|
cb929cb329
|
Fix housekeeping spi tests
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2022-10-02 05:37:27 -07:00 |
M0stafaRady
|
bc9eb2eb31
|
Update README.md
|
2022-10-02 14:35:49 +02:00 |
M0stafaRady
|
928fc6a2a5
|
Update README.md
|
2022-10-02 14:27:42 +02:00 |
M0stafaRady
|
a0da0fc906
|
add photo of cocotb structure
|
2022-10-02 14:10:17 +02:00 |
M0stafaRady
|
ad053568e7
|
Create README.md
add READme in doc file
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2022-10-02 14:09:49 +02:00 |
M0stafaRady
|
bd712f64d4
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rename cocotb.py to verify_cocotb.py
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2022-10-02 04:29:48 -07:00 |
M0stafaRady
|
b5fb97e5f4
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rename run.py to cocotb.py
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2022-10-02 04:22:44 -07:00 |
M0stafaRady
|
9e0be5473d
|
remove hex files from directory
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2022-10-02 04:20:32 -07:00 |
M0stafaRady
|
1c48f527b8
|
add bitbang_spi_o tests
|
2022-10-01 12:39:54 -07:00 |
M0stafaRady
|
199d5c0f5c
|
fix bug assert csb before reset for the GL sim to work
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2022-10-01 12:36:02 -07:00 |
M0stafaRady
|
53e868abdf
|
add clock to the output od configuration function
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2022-10-01 12:34:53 -07:00 |
M0stafaRady
|
d12fac2ad1
|
update run script to delete vcs files before test run
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2022-10-01 12:28:52 -07:00 |
M0stafaRady
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555488c832
|
fix timeout values to the passing number of cycles required + 10%
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2022-10-01 04:11:46 -07:00 |
M0stafaRady
|
9615629a42
|
fix bug bit time calculation
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2022-10-01 02:53:24 -07:00 |
M0stafaRady
|
68c88b116a
|
increase the clock period to 25ns
|
2022-10-01 02:52:30 -07:00 |
M0stafaRady
|
18b4f36525
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add test uart_rx
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2022-10-01 02:23:47 -07:00 |
M0stafaRady
|
407b0be306
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Update script to return fatal error when hex generation fails
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2022-10-01 01:48:55 -07:00 |
M0stafaRady
|
f2ca45358b
|
remove AN.DB folder from git hub
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2022-09-30 03:52:34 -07:00 |
M0stafaRady
|
7546ce10c7
|
simple readme
|
2022-09-30 03:52:34 -07:00 |
M0stafaRady
|
add4c5f6c8
|
Adding cocotb evironment with tests and scripts to run
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2022-09-30 03:52:34 -07:00 |