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fix some timeout and errors due to cpu became slower and sram interface are deleted

This commit is contained in:
M0stafaRady 2022-10-11 14:00:49 -07:00
parent bd40646465
commit 2a5c7b876b
6 changed files with 14 additions and 16 deletions
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2
verilog/dv/cocotb/tests/bitbang/bitbang_spi_i.c
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@ -50,7 +50,7 @@ void main()
reg_mprj_io_0 = GPIO_MODE_MGMT_STD_INPUT_NOPULL;
reg_debug_1 = 0xFF; // finish configuration
while (reg_debug_2 != 0xDD);
reg_debug_1 = 0XAA; // configuration done wait environment to send 0x8F66FD7B to reg_mprj_datal
while (reg_mprj_datal != 0x8F66FD7B);
reg_debug_1 = 0XBB; // configuration done wait environment to send 0xFFA88C5A to reg_mprj_datal

2
verilog/dv/cocotb/tests/bitbang/bitbang_tests.py
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@ -234,7 +234,7 @@ async def bitbang_no_cpu_all_i(dut):
"""Testbench of GPIO configuration through bit-bang method using the StriVe housekeeping SPI."""
"""Testbench of GPIO configuration through bit-bang method using the housekeeping SPI."""
@cocotb.test()
@repot_test
async def io_ports(dut):

10
verilog/dv/cocotb/tests/bitbang/bitbang_tests_cpu.py
View File

@ -113,7 +113,7 @@ async def bitbang_cpu_all_01(dut):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_0011(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
caravelEnv,clock = await test_configure(dut,timeout_cycles=5963970)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -134,7 +134,7 @@ async def bitbang_cpu_all_0011(dut):
@cocotb.test()
@repot_test
async def bitbang_cpu_all_1100(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=5065204)
caravelEnv,clock = await test_configure(dut,timeout_cycles=5962067)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -224,7 +224,7 @@ async def bitbang_cpu_all_i(dut):
@cocotb.test()
@repot_test
async def bitbang_spi_o(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=639757)
caravelEnv,clock = await test_configure(dut,timeout_cycles=2639757)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -289,7 +289,7 @@ async def bitbang_spi_o(dut):
@cocotb.test()
@repot_test
async def bitbang_spi_i(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=56703)
caravelEnv,clock = await test_configure(dut,timeout_cycles=11156703)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()
@ -316,7 +316,7 @@ async def bitbang_spi_i(dut):
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 1 and 36
await clock_in_right_i_left_i_standard_spi(caravelEnv,0) # 0 and 37
await load_spi(caravelEnv) # load
cpu.write_debug_reg2_backdoor(0xDD)
await wait_reg1(cpu,caravelEnv,0xAA)
cocotb.log.info(f"[TEST] configuration finished")
data_in = 0x8F66FD7B

2
verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py
View File

@ -91,7 +91,7 @@ async def calculate_clk_period(clk,name):
@cocotb.test()
@repot_test
async def hk_disable(dut):
caravelEnv,clock = await test_configure(dut,timeout_cycles=11243)
caravelEnv,clock = await test_configure(dut,timeout_cycles=3598)
cpu = RiskV(dut)
cpu.cpu_force_reset()
cpu.cpu_release_reset()

4
verilog/dv/cocotb/tests/housekeeping/housekeeping_regs/housekeeping_regs_tests.py
View File

@ -110,10 +110,10 @@ async def hk_regs_wr_spi(dut):
if key == 'base_addr':
continue
address = regs[mem][key][0][7]
if address in [111,36]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled
if address in [111,36,10]: # 111 is for Housekeeping SPI disable, writing 1 to this address will disable the SPI and 36 is for mprj_io[03] changing bit 3 of this register would disable the spi by deassert spi_is_enabled and 10 0xa cpu irq is self resetting
continue
# address = int(key,16)
if address in [0x69,0x6A,0x6B,0x6C]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
if address in [0x69,0x6A,0x6B,0x6C,0x6D]: # skip testing reg_mprj_datal and reg_mprj_datah because when reading them it's getting the gpio input value
continue
data_in = random.getrandbits(bits_num)
cocotb.log.info(f"[TEST] Writing {bin(data_in)} to reg [{regs[mem][key][0][0]}] address {hex(address)} through SPI")

10
verilog/dv/cocotb/wb_models/housekeepingWB/HK_regs.json
View File

@ -1,7 +1,7 @@
{
"_comment": "the list contain the fields in register with shift spcified [field name,name iniside housekeeping, shift, size,mode,reset,value(intial is reset value), SPI address map] the shift is from the base address like SPI, system and gpio base address",
"_comment2": "Base address is the first element and called first address",
"_not_used_currently":["0x34",[["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]], "0x30",[["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]],
"SPI":{ "base_addr": ["SPI_BASE_ADR",638582784],
"0x00": [["SPI status",null,0,8,"undefined",0,0,0]],
@ -22,9 +22,7 @@
"0x1e": [["DCO trim",["pll_trim",23,16],0,8,"RW",255,255,15]],
"0x1f": [["DCO trim",["pll_trim",25,24],0,2,"RW",3,3,16]],
"0x20": [["PLL output divider","pll_sel",0,3,"RW",2,2,17],["PLL output divider 2","pll90_sel",3,3,"RW",2,2,17]],
"0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]],
"0x34": [["SRAM read-only control","sram_ro_csb",0,1,"RW",1,1,20],["SRAM read-only control","sram_ro_clk",1,1,"RW",0,0,20]],
"0x30": [["SRAM read-only address","sram_ro_addr",0,8,"RW",0,0,21]]
"0x24": [["PLL feedback divider","pll_div",0,5,"RW",4,4,18]]
},
"GPIO":{ "base_addr": ["GPIO_BASE_ADR",637534208],
@ -44,8 +42,8 @@
"0x29": [["mprj_io[01](reg_mprj_io_1)",["gpio_configure[1]",12,8],0,5,"RW",24,24,31]],
"0x2c": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",7,0],0,8,"RW",3,3,34]],
"0x2d": [["mprj_io[02](reg_mprj_io_2)",["gpio_configure[2]",12,8],0,5,"RW",4,4,33]],
"0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",3,3,36]],
"0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",4,4,35]],
"0x30": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",7,0],0,8,"RW",1,1,36]],
"0x31": [["mprj_io[03](reg_mprj_io_3)",["gpio_configure[3]",12,8],0,5,"RW",8,8,35]],
"0x34": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",7,0],0,8,"RW",3,3,38]],
"0x35": [["mprj_io[04](reg_mprj_io_4)",["gpio_configure[4]",12,8],0,5,"RW",4,4,37]],
"0x38": [["mprj_io[05](reg_mprj_io_5)",["gpio_configure[5]",7,0],0,8,"RW",3,3,40]],