IO[0] affects the uart selecting btw system and debug

2022-10-05 13:47:23 -07:00 · 2022-10-05 13:47:23 -07:00 · b31efbdeea
parent fca511f306
commit b31efbdeea
1 changed files with 1 additions and 0 deletions
--- a/verilog/dv/cocotb/tests/uart/uart.py
+++ b/verilog/dv/cocotb/tests/uart/uart.py
@ -66,6 +66,7 @@ async def uart_rx(dut):
    cpu.cpu_force_reset()
    cpu.cpu_release_reset()
    cocotb.log.info(f"[TEST] Start uart test")  
+    caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug
    caravelEnv.drive_gpio_in((5,5),1)
    # calculate bit time
    clk = clock.period/1000