From b31efbdeeab875c3bb0c5b56b977a96b9c9d616d Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Wed, 5 Oct 2022 13:47:23 -0700 Subject: [PATCH] IO[0] affects the uart selecting btw system and debug --- verilog/dv/cocotb/tests/uart/uart.py | 1 + 1 file changed, 1 insertion(+) diff --git a/verilog/dv/cocotb/tests/uart/uart.py b/verilog/dv/cocotb/tests/uart/uart.py index 1e86e100..0cf6eb79 100644 --- a/verilog/dv/cocotb/tests/uart/uart.py +++ b/verilog/dv/cocotb/tests/uart/uart.py @@ -66,6 +66,7 @@ async def uart_rx(dut): cpu.cpu_force_reset() cpu.cpu_release_reset() cocotb.log.info(f"[TEST] Start uart test") + caravelEnv.drive_gpio_in((0,0),0) # IO[0] affects the uart selecting btw system and debug caravelEnv.drive_gpio_in((5,5),1) # calculate bit time clk = clock.period/1000