mirror of https://github.com/efabless/caravel.git
Add test hk_disable
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28b453783f
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@ -227,5 +227,12 @@
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"GL":["r_gl","nightly","weekly","tape_out"],
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"GL_SDF":["r_sdf","weekly","tape_out"],
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"description":"check clock redirect is working as expected"}
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,"hk_disable" :{"level":0,
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"SW":true,
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"RTL":["r_rtl","setup","nightly","weekly","tape_out"],
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"GL":["r_gl","nightly","weekly","tape_out"],
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"GL_SDF":["r_sdf","weekly","tape_out"],
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"description":"check Housekeeping SPI disable register is working"}
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}
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}
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@ -15,4 +15,4 @@ void main(){
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while (reg_mprj_xfer == 1);
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reg_debug_1 =0xAA;
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return;
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}
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}
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@ -0,0 +1,14 @@
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#include <defs.h>
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#include <stub.c>
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// --------------------------------------------------------
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void main(){
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reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2
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reg_debug_1 = 0x0;
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reg_debug_2 = 0xBB;
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while (reg_debug_1 != 0xAA);
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reg_hkspi_disable = 0;
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// reg_hkspi_pll_ena =0;
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reg_debug_1 =0xBB;
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}
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@ -1,3 +1,4 @@
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from faulthandler import disable
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import random
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import cocotb
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from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles
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@ -18,7 +19,7 @@ core_clock = 0
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@cocotb.test()
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@repot_test
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async def clock_redirect(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=264012)
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caravelEnv,clock = await test_configure(dut,timeout_cycles=13060)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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@ -86,3 +87,61 @@ async def calculate_clk_period(clk,name):
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core_clock = val
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return val
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@cocotb.test()
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@repot_test
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async def hk_disable(dut):
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caravelEnv,clock = await test_configure(dut,timeout_cycles=11243)
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cpu = RiskV(dut)
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cpu.cpu_force_reset()
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cpu.cpu_release_reset()
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# check spi working by writing to PLL enables
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old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
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await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
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pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
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if pll_enable == 1-old_pll_enable:
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cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}")
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else:
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cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
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old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
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await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
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pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
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if pll_enable == 1-old_pll_enable:
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cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}")
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else:
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cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}")
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# disable Housekeeping SPIca
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await write_reg_spi(caravelEnv,0x6f,0x1)
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# try to change pll_en
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old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
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await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
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pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
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if pll_enable == 1-old_pll_enable:
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cocotb.log.error(f"[TEST] Error: SPI swap pll_enable value from {old_pll_enable} to {pll_enable} while housekeeping spi is disabled")
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else:
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cocotb.log.info(f"[TEST] pass: SPI isn't working when SPI housekeeping is disabled")
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# enable SPI housekeeping through firmware
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await wait_reg2(cpu,caravelEnv,0xBB) # start waiting on reg1 AA
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cpu.write_debug_reg1_backdoor(0xAA)
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await wait_reg1(cpu,caravelEnv,0xBB) # enabled the housekeeping
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old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}")
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await write_reg_spi(caravelEnv,0x8,1-old_pll_enable)
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pll_enable = dut.uut.housekeeping.pll_ena.value.integer
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cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}")
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if pll_enable == 1-old_pll_enable:
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cocotb.log.info(f"[TEST] Pass: Housekeeping SPI has been enabled correctly through firmware")
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else:
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cocotb.log.error(f"[TEST] Error: Housekeeping SPI failed to be enabled through firmware")
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