From 7e407e115591a81f5e70c306f4f10d75f3624283 Mon Sep 17 00:00:00 2001 From: M0stafaRady Date: Thu, 6 Oct 2022 10:12:12 -0700 Subject: [PATCH] Add test hk_disable --- verilog/dv/cocotb/tests.json | 7 +++ .../housekeeping/general/clock_redirect.c | 2 +- .../tests/housekeeping/general/hk_disable.c | 14 +++++ .../tests/housekeeping/general/sys_ctrl.py | 61 ++++++++++++++++++- 4 files changed, 82 insertions(+), 2 deletions(-) create mode 100644 verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c diff --git a/verilog/dv/cocotb/tests.json b/verilog/dv/cocotb/tests.json index 22f5f9e5..116828ca 100644 --- a/verilog/dv/cocotb/tests.json +++ b/verilog/dv/cocotb/tests.json @@ -227,5 +227,12 @@ "GL":["r_gl","nightly","weekly","tape_out"], "GL_SDF":["r_sdf","weekly","tape_out"], "description":"check clock redirect is working as expected"} + + ,"hk_disable" :{"level":0, + "SW":true, + "RTL":["r_rtl","setup","nightly","weekly","tape_out"], + "GL":["r_gl","nightly","weekly","tape_out"], + "GL_SDF":["r_sdf","weekly","tape_out"], + "description":"check Housekeeping SPI disable register is working"} } } \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c b/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c index 19ec69e9..7dbba8d2 100644 --- a/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c +++ b/verilog/dv/cocotb/tests/housekeeping/general/clock_redirect.c @@ -15,4 +15,4 @@ void main(){ while (reg_mprj_xfer == 1); reg_debug_1 =0xAA; return; - } \ No newline at end of file +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c b/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c new file mode 100644 index 00000000..fb9e808a --- /dev/null +++ b/verilog/dv/cocotb/tests/housekeeping/general/hk_disable.c @@ -0,0 +1,14 @@ +#include +#include +// -------------------------------------------------------- + +void main(){ + reg_wb_enable =1; // for enable writing to reg_debug_1 and reg_debug_2 + reg_debug_1 = 0x0; + reg_debug_2 = 0xBB; + + while (reg_debug_1 != 0xAA); + reg_hkspi_disable = 0; + // reg_hkspi_pll_ena =0; + reg_debug_1 =0xBB; +} \ No newline at end of file diff --git a/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py index bccc0f53..b6c5a42f 100644 --- a/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py +++ b/verilog/dv/cocotb/tests/housekeeping/general/sys_ctrl.py @@ -1,3 +1,4 @@ +from faulthandler import disable import random import cocotb from cocotb.triggers import FallingEdge,RisingEdge,ClockCycles @@ -18,7 +19,7 @@ core_clock = 0 @cocotb.test() @repot_test async def clock_redirect(dut): - caravelEnv,clock = await test_configure(dut,timeout_cycles=264012) + caravelEnv,clock = await test_configure(dut,timeout_cycles=13060) cpu = RiskV(dut) cpu.cpu_force_reset() cpu.cpu_release_reset() @@ -86,3 +87,61 @@ async def calculate_clk_period(clk,name): core_clock = val return val + +@cocotb.test() +@repot_test +async def hk_disable(dut): + caravelEnv,clock = await test_configure(dut,timeout_cycles=11243) + cpu = RiskV(dut) + cpu.cpu_force_reset() + cpu.cpu_release_reset() + + # check spi working by writing to PLL enables + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}") + else: + cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}") + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.info(f"[TEST] Pass: SPI swap pll_enable value from {old_pll_enable} to {pll_enable}") + else: + cocotb.log.error(f"[TEST] Error: SPI isn't working correctly it cant change pll from {old_pll_enable} to {1-old_pll_enable}") + + # disable Housekeeping SPIca + await write_reg_spi(caravelEnv,0x6f,0x1) + + # try to change pll_en + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.error(f"[TEST] Error: SPI swap pll_enable value from {old_pll_enable} to {pll_enable} while housekeeping spi is disabled") + else: + cocotb.log.info(f"[TEST] pass: SPI isn't working when SPI housekeeping is disabled") + + # enable SPI housekeeping through firmware + await wait_reg2(cpu,caravelEnv,0xBB) # start waiting on reg1 AA + cpu.write_debug_reg1_backdoor(0xAA) + await wait_reg1(cpu,caravelEnv,0xBB) # enabled the housekeeping + + old_pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {old_pll_enable}") + await write_reg_spi(caravelEnv,0x8,1-old_pll_enable) + pll_enable = dut.uut.housekeeping.pll_ena.value.integer + cocotb.log.debug(f"[TEST] pll_enable = {pll_enable}") + if pll_enable == 1-old_pll_enable: + cocotb.log.info(f"[TEST] Pass: Housekeeping SPI has been enabled correctly through firmware") + else: + cocotb.log.error(f"[TEST] Error: Housekeeping SPI failed to be enabled through firmware") + \ No newline at end of file