Commit Graph

224 Commits

Author SHA1 Message Date
tangxifan 4423d917fa [core] debugging 2023-03-03 18:00:43 -08:00
tangxifan 29ee6e7136 [core] debugging 2023-03-03 17:33:53 -08:00
tangxifan 98d8c75d86 [code] format 2023-03-02 21:36:08 -08:00
tangxifan 02b50e3464 [lib] now clock spine requires explicit definition of track type and direction when coordinate is vague 2023-03-02 21:33:32 -08:00
tangxifan 46510388be [core] now fabric generator can wire clock ports to routing blocks 2023-03-02 12:33:26 -08:00
tangxifan 099d9f32f4 [core] dev 2023-03-01 16:08:15 -08:00
tangxifan 60ff298987 [lib] add new feature to enable clock tree connection to global ports of tiles 2023-02-28 22:36:41 -08:00
tangxifan 2ff8fb8737 [core] wrapping up clock routing command 2023-02-28 16:52:54 -08:00
tangxifan 8d5c21b14d [core] code format 2023-02-27 23:00:15 -08:00
tangxifan 2735b708d3 [core] reworked the tapping XML syntax 2023-02-27 22:59:44 -08:00
tangxifan ff69664c14 [core] syntax 2023-02-27 22:39:12 -08:00
tangxifan d4e19edc71 [core] finishing up clock rr_graph appending 2023-02-27 22:31:16 -08:00
tangxifan 9f20d2e639 [lib] now clock arch supports tap points 2023-02-27 22:06:13 -08:00
tangxifan 3a40c5e15f [lib] update example of clock arch definition 2023-02-27 21:49:14 -08:00
tangxifan 7d0c23c675 [lib] new api for lowest level clock connections 2023-02-27 15:16:23 -08:00
tangxifan b3dec93eb9 [core] code format 2023-02-27 15:12:59 -08:00
tangxifan 9ec4d690db [core] clock edges interconnecting clock tracks across levels 2023-02-27 15:10:36 -08:00
tangxifan b6eace8fac [core] now switch id is linked in clock network 2023-02-27 13:10:54 -08:00
tangxifan 009d711ba5 [core] code format 2023-02-26 22:23:41 -08:00
tangxifan 87a9146082 [core] adding rr spatial lookup for clock nodes only 2023-02-26 22:23:17 -08:00
tangxifan db36f87dfa [core] enhance clock tree arch validation 2023-02-26 18:39:53 -08:00
tangxifan 780fc0f26d [core] developing validators and annotate rr_segment for clock arch 2023-02-26 18:03:55 -08:00
tangxifan 75773ddd4e [code] format 2023-02-26 12:46:29 -08:00
tangxifan 3db5acfb37 [core] dev 2023-02-26 12:40:13 -08:00
tangxifan 8f0d94ba73 [code] format 2023-02-25 22:43:21 -08:00
tangxifan 0b33650761 [core] dev 2023-02-25 22:41:33 -08:00
tangxifan 7f07a9d031 [lib] add default seg/switch to clock arch. Fixed syntax 2023-02-24 19:15:39 -08:00
tangxifan 65b27a3377 [lib] fixed a few bugs 2023-02-22 21:29:18 -08:00
tangxifan 40f6b5a3fe [lib] fixed a few bugs 2023-02-22 21:23:08 -08:00
tangxifan a9d5e4dfbd [lib] update example clock arch xml 2023-02-22 21:18:00 -08:00
tangxifan d1133000ba [lib] code format 2023-02-22 21:03:04 -08:00
tangxifan aafd1e6fb3 [lib] syntax 2023-02-22 21:02:35 -08:00
tangxifan b2ef1db5f4 [lib] finishing up code changes; start debugging 2023-02-22 20:46:18 -08:00
tangxifan 1c8a5eb098 [lib] adding linker 2023-02-22 20:29:32 -08:00
tangxifan bf2876c60e [lib] developing linker 2023-02-22 18:36:22 -08:00
tangxifan ce20a16aad [lib] adding unit test 2023-02-22 18:26:18 -08:00
tangxifan b37deb4b02 [lib] adding writer 2023-02-22 18:21:28 -08:00
tangxifan 5cd310c4cc [lib] adding missing apis 2023-02-22 15:04:52 -08:00
tangxifan 7bc843b74a [lib] developing xml parser for clk arch 2023-02-22 13:23:09 -08:00
tangxifan 25e43b47da [lib] first round of data structure on clock arch 2023-02-22 12:18:44 -08:00
tangxifan 9eb2374bc6 [lib] developing 2023-02-21 22:29:25 -08:00
tangxifan fe594acab1 [lib] adding clock network data structure 2023-02-21 16:53:05 -08:00
tangxifan e7fc065032 [lib] start developing clock arch data structure and I/O 2023-02-21 15:06:35 -08:00
tangxifan ac8c0e243c [core] code format 2023-01-15 12:13:59 -08:00
tangxifan cab7e04901 [core] fixed a bug in repacker to avoid routing constrained nets 2023-01-15 12:13:12 -08:00
tangxifan ff0a4dfccb [lib] format 2023-01-08 22:41:07 -08:00
tangxifan aec592b27e [lib] now shell forbids to call any hidden commands from interactive mode or script mode 2023-01-08 22:34:35 -08:00
tangxifan da7153f031 [lib] typo which causes shell show hidden commands mistakenly 2023-01-08 21:43:35 -08:00
tangxifan b569d6b603 [core] format 2023-01-07 11:40:17 -08:00
tangxifan d2632b17cd [lib] bug 2023-01-07 11:39:26 -08:00
tangxifan c7a4d25e35 [core] now all the commands can be optionally hidden 2023-01-07 11:36:10 -08:00
tangxifan 7028c1ec72 [lib] now openfpga shell supports a new type of executive functions 2023-01-07 11:17:02 -08:00
tangxifan 77b64a21d4 [lib] format 2023-01-02 12:41:24 -08:00
tangxifan 994402ec9a [engine] move shell cmd split function to openfpga tokenizer 2023-01-02 12:38:16 -08:00
tangxifan faff254808 [lib] now command line supports pairs of "" where users can define a long string with spaces inside 2023-01-01 11:56:58 -08:00
tangxifan 76570e653c [engine] format 2023-01-01 10:23:18 -08:00
tangxifan c90f8389f1 [engine] debugged 2023-01-01 10:22:47 -08:00
tangxifan 8d947c7bdb [engine] now developers can write their superset command based on other commands through openfpga shell 2023-01-01 10:10:09 -08:00
tangxifan cfedc547d9 [lib] code format 2022-12-31 23:39:05 -08:00
tangxifan 50aec6ec62 [lib] add exec command as a pre-defined one in shell 2022-12-31 23:37:38 -08:00
tangxifan 6e3ea51a06 [lib] now openfpga shell supports 'source <script>' command 2022-12-31 22:22:30 -08:00
tangxifan c9c410826d [lib] replace hardcoded name with shell name 2022-12-30 11:58:45 -08:00
tangxifan 24a174c7a4 [engine] fixed syntax errors 2022-11-23 17:06:27 -08:00
tangxifan 07424b1e7f [engine] now main() is encapuslated in a class OpenfpgaShell 2022-11-23 16:52:22 -08:00
tangxifan 2d42826919 [lib] code format 2022-10-21 13:03:03 -07:00
tangxifan 0999c9444b [lib] remove debugging messages 2022-10-21 12:44:56 -07:00
tangxifan b720b49eb1 [lib] now count pcf errors 2022-10-21 11:48:09 -07:00
tangxifan c9631497e2 [engine] syntax 2022-10-17 16:11:49 -07:00
tangxifan 60c448c98d [engine] syntax 2022-10-17 15:49:34 -07:00
tangxifan 76862efa57 [engine] syntax 2022-10-17 15:46:19 -07:00
tangxifan c3f180372d [engine] do not error out when ql-style is used in pin table 2022-10-17 15:42:22 -07:00
tangxifan 0f2b8da7f0 [engine] code format 2022-10-17 14:55:34 -07:00
tangxifan 63d8b00630 [engine] syntax 2022-10-17 14:54:18 -07:00
tangxifan 811438c20e [engine] syntax 2022-10-17 14:20:23 -07:00
tangxifan 11624cd0c6 [engine] enabling new feature: pin_table_direction_convention 2022-10-17 14:08:21 -07:00
tangxifan 2f434fd4d3 [lib] developing pin dir convention support 2022-10-17 12:35:06 -07:00
tangxifan dbbabbc098 [lib] developing the support on forcing pin direction from a specific column in pin table .csv 2022-10-17 12:23:39 -07:00
tangxifan e2debd2dde [engine] add missing header files after coding formatter sorts the include files 2022-10-06 18:08:57 -07:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan cc6bf85433 [cmake] now rename version to short 'OPENFPGA_ENABLE_VERSION' 2022-10-03 11:37:41 -07:00
tangxifan a144794ce6 [cmake] skip custom build on version build with an option 2022-10-03 11:18:43 -07:00
tangxifan 81e524cec4 [CMake] Added a new option 'OPENFPGA_WITH_VERSION_UP_TO_DATE' which allows users to skip version build (by default it remains always on) 2022-10-03 11:11:21 -07:00
tangxifan 25f6c529e0 [engine] fixed syntax errors when using clang 2022-08-25 09:58:43 -07:00
tangxifan a50392f380 [script] update CMakefile to streamline test source files 2022-08-24 19:56:35 -07:00
tangxifan 83600d2bdd [script] add install target for lib CMakefile 2022-08-24 19:47:01 -07:00
tangxifan 5d6a90d983 [engine] remove compile warnings 2022-08-22 20:59:50 -07:00
tangxifan d5f56aada3 [lib] typo 2022-08-22 18:29:20 -07:00
tangxifan 903dd6cef6 [engine] remove warnings 2022-08-18 15:56:18 -07:00
tangxifan 2d05462219 [lib] remove warnings 2022-08-18 15:53:51 -07:00
tangxifan 2957b3aa7f [lib] remove useless header files 2022-08-18 15:40:29 -07:00
tangxifan a52597361b [script] remove duplicated libraries in dependency list for some libopenfpga 2022-08-18 11:34:01 -07:00
tangxifan e909f4fabe [lib] rename libopenfpga to libs 2022-08-18 10:27:20 -07:00
tangxifan 075900a7c9 [engine] remove out-of-date codes due to the upgrades in VTR submodule 2022-08-16 13:56:08 -07:00
coolbreeze413 9fd8c02e13 header inclusions required for MinGW windows build 2022-06-29 07:03:38 +05:30
Manadher Kharroubi 73d9b40124 adding Tcl interface to vpr 2022-06-07 09:15:20 -07:00
Szymon Kulis c4e033ac9b Include limits in argparse.cpp 2021-11-28 07:57:31 +01:00
tangxifan 1d96974b99 [Tool] Patch to remove compiler warnings 2021-02-04 16:54:04 -07:00
tangxifan 2483154c34 [Tool] Patch disable_packing XML syntax to be consistent with VPR upstream 2021-02-04 16:28:32 -07:00
tangxifan dd4f83a374 bug fixing to constant string to display interconnect names 2020-04-07 18:28:19 -06:00
tangxifan 13cd48c119 add support on packable/unpackable modes in VPR architecture 2020-04-06 16:07:49 -06:00
tangxifan 610c71671f experimentally developing through channels inside multi-width and multi-height grids.
Still debugging.
2020-03-24 16:47:45 -06:00
tangxifan 708fda9606 fixed a bug in using tileable routing when directlist is enabled 2020-03-20 16:38:58 -06:00
tangxifan a0b150f12e adding micro architecture using adder chain 2020-03-20 14:18:59 -06:00
tangxifan 5be118d695 tileable rr_graph builder ready to debug 2020-03-06 16:18:45 -07:00
tangxifan 2d86a02358 refactored LUT bitstream generation to use vtr logic 2020-02-25 12:45:13 -07:00
tangxifan 5006a4395d bring RRGraph object and writer online 2020-01-31 16:39:40 -07:00
tangxifan 9269d7106d move rr_graph back to vpr because the reader and writer requires too much dependency on the core engine 2020-01-31 15:42:44 -07:00
tangxifan fb0bcd7a48 create rr_graph library to enforce unit test on the new data structures as well as compare to legacy rr_node 2020-01-31 12:29:50 -07:00
tangxifan 75c3507acf add verbose output option for openfpga linking architecture 2020-01-31 11:36:58 -07:00
tangxifan 8a7a4dc48e add physical type annotation for interconnects and inference 2020-01-28 21:59:10 -07:00
tangxifan 5ecb771673 debugging the annotation to physical mode of pb_types 2020-01-27 17:43:22 -07:00
tangxifan a6fbbce33e start developing the openfpga arch binding to vpr 2020-01-27 15:31:12 -07:00
tangxifan 48ecb6e48b immigrate XML parser for circuit_lib to library readarchopenfpga 2020-01-12 18:11:00 -07:00
tangxifan 2901a6eec5 add missing tatum file due to the folder name tags is in the git ignore list!!! 2020-01-03 23:13:49 -05:00
tangxifan 60cbcf9104 add missing tatum 2020-01-03 22:42:17 -05:00
tangxifan 7a96f866bb remove tatum temporarily 2020-01-03 22:41:49 -05:00
tangxifan f1bafffa87 add vpr8 libs and core engine for further integration 2020-01-03 16:14:42 -07:00
tangxifan f70f387f9f minor tuning on ini compilation 2019-11-01 20:51:49 -06:00
tangxifan 3669a47d3b reworked the ini writer 2019-11-01 20:25:01 -06:00
Ganesh Gore a3e9b4aea9 Added mINI/lib - INI Read write to project 2019-09-27 13:58:48 -06:00
tangxifan 2c7d6e3de4 adding port parsers 2019-08-09 17:48:55 -06:00
tangxifan ad8c33e1ba complete the mutators 2019-08-08 11:33:11 -06:00
tangxifan 38962c4607 adding member functions for circuit library 2019-08-07 15:45:27 -06:00
tangxifan 44d21ebb90 fixed a bug in Verilog generator supporting SRAM5T 2019-06-13 14:42:39 -06:00