[lib] rename libopenfpga to libs
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@ -153,7 +153,6 @@ endforeach()
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#
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# Sanitizer flags
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#
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set(SANITIZE_FLAGS "")
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if(OPENFPGA_ENABLE_SANITIZE)
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#Enable sanitizers
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@ -197,10 +196,8 @@ endif()
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#
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# Sub-projects
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#
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#add_subdirectory(iverilog)
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add_subdirectory(libopenfpga)
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#add_subdirectory(yosys)
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add_subdirectory(vtr-verilog-to-routing)
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add_subdirectory(libs)
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add_subdirectory(openfpga)
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# yosys compilation starts
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