tangxifan
|
a15db83267
|
[core] code format
|
2023-09-26 11:41:11 -07:00 |
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tangxifan
|
ea91182216
|
[core] check option conflicts
|
2023-09-26 11:40:42 -07:00 |
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tangxifan
|
c4bce834e4
|
[core] code format
|
2023-09-25 22:34:39 -07:00 |
|
tangxifan
|
5aa206e616
|
[core] fixed some bugs
|
2023-09-25 22:27:24 -07:00 |
|
tangxifan
|
1624dc9764
|
[core] code format
|
2023-09-25 21:13:50 -07:00 |
|
tangxifan
|
76f446caec
|
[core] fixed a bug
|
2023-09-25 21:13:11 -07:00 |
|
tangxifan
|
dbd466cdec
|
[core] now support tile port merge
|
2023-09-25 18:16:24 -07:00 |
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tangxifan
|
3adf81046a
|
[core] code format
|
2023-09-25 17:22:26 -07:00 |
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tangxifan
|
5e269e8bc4
|
[core] support port merging at grid modules
|
2023-09-25 17:21:58 -07:00 |
|
tangxifan
|
edb0e687f1
|
[core] code format
|
2023-09-23 12:15:53 -07:00 |
|
tangxifan
|
11de8965a8
|
[core] fixed some bugs
|
2023-09-23 12:15:31 -07:00 |
|
tangxifan
|
860cfd53c6
|
[core] fixed critical bugs in renaming modules
|
2023-09-23 11:51:31 -07:00 |
|
tangxifan
|
ca3617a029
|
[core] code format
|
2023-09-20 20:37:27 -07:00 |
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tangxifan
|
1ef38b6a64
|
[core] now name the port of tiles using the relative index of the subblocks in each tile, rather than the unique index of subblocks across a complete fabric. This avoids all the conflicts in naming
|
2023-09-20 20:34:21 -07:00 |
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tangxifan
|
c105b56bf0
|
[core] code format
|
2023-09-18 23:31:27 -07:00 |
|
tangxifan
|
43fd08a3fe
|
[core] fixed a bug
|
2023-09-18 23:31:09 -07:00 |
|
tangxifan
|
4d11f73471
|
[core] fixed a bug
|
2023-09-18 20:43:15 -07:00 |
|
tangxifan
|
a1e609c901
|
[core] fixed some bugs
|
2023-09-18 16:39:07 -07:00 |
|
tangxifan
|
1daabb990e
|
[core] code format
|
2023-09-18 15:35:13 -07:00 |
|
tangxifan
|
110301a2e4
|
[core] now tile port naming can follow index
|
2023-09-18 15:34:40 -07:00 |
|
tangxifan
|
e46e58527a
|
[core] code format
|
2023-09-17 23:16:38 -07:00 |
|
tangxifan
|
eeb1bd6662
|
[core] fixed some bugs
|
2023-09-17 23:16:15 -07:00 |
|
tangxifan
|
c6175aa514
|
[core] code format
|
2023-09-17 22:37:48 -07:00 |
|
tangxifan
|
ef97127c63
|
[core] fixed some bugs in testbenches when renaming top modules
|
2023-09-17 22:34:00 -07:00 |
|
tangxifan
|
c14277a674
|
[core] fixing bugs
|
2023-09-17 17:57:57 -07:00 |
|
tangxifan
|
d5152dc16d
|
[core] fixed a bug on the hierarchy writer
|
2023-09-17 17:42:25 -07:00 |
|
tangxifan
|
4ccb4737be
|
[core] code format
|
2023-09-17 17:33:10 -07:00 |
|
tangxifan
|
f79da76656
|
[core] supporting renaming on all the verilog modules
|
2023-09-17 17:29:11 -07:00 |
|
tangxifan
|
72a3c05747
|
[core] code format
|
2023-09-17 13:29:30 -07:00 |
|
tangxifan
|
ccd4c1861b
|
[core] developing new command to write module naming rules
|
2023-09-16 19:37:06 -07:00 |
|
tangxifan
|
32df673d72
|
[core] code format
|
2023-09-16 18:35:33 -07:00 |
|
tangxifan
|
200ecad74a
|
[core] fixed bugs in bitgen
|
2023-09-16 18:34:55 -07:00 |
|
tangxifan
|
058bb1ef51
|
[core] code format
|
2023-09-16 18:24:38 -07:00 |
|
tangxifan
|
6fc2924438
|
[core] syntax
|
2023-09-16 18:16:30 -07:00 |
|
tangxifan
|
d61d88f12e
|
[core] fixed some bugs in verilog writer due to renaming
|
2023-09-16 18:13:22 -07:00 |
|
tangxifan
|
37573abc22
|
[core] code format
|
2023-09-15 23:32:40 -07:00 |
|
tangxifan
|
c85c64eb5a
|
[core] syntax
|
2023-09-15 23:30:34 -07:00 |
|
tangxifan
|
bc407e5d69
|
[core] code complete for rename modules
|
2023-09-15 23:22:31 -07:00 |
|
tangxifan
|
2a45b49890
|
[core] developing renaming commands. options and functions
|
2023-09-15 19:15:18 -07:00 |
|
tangxifan
|
af67b02cca
|
[lib] rename lib to namemanager as a unified library to provide naming support on FPGA modules
|
2023-09-15 13:51:14 -07:00 |
|
tangxifan
|
eaadff3448
|
[core] fixed some bugs
|
2023-09-06 22:49:56 -07:00 |
|
tangxifan
|
bcb82d43af
|
[core] code format
|
2023-09-06 22:40:59 -07:00 |
|
tangxifan
|
2fee56548b
|
[core] fixed some bugs
|
2023-09-06 22:39:59 -07:00 |
|
tangxifan
|
f544953085
|
[core] code format
|
2023-09-06 22:29:30 -07:00 |
|
tangxifan
|
f8b2eec988
|
[core] now default net type wire will not appear. timescale does not show in fabric netlists
|
2023-09-06 22:27:51 -07:00 |
|
tangxifan
|
539bcba851
|
[core] now default nettype is reverted to 'wire' at the end of each module; Being compatible with Verilog 2001 standard; Avoid unnecessary impacts on netlists which do not explicitly define default net types
|
2023-09-06 17:23:41 -07:00 |
|
tangxifan
|
dfe5447e2a
|
[core] format
|
2023-08-25 15:21:24 -07:00 |
|
tangxifan
|
b8c66b06a0
|
[core] syntax
|
2023-08-25 15:17:52 -07:00 |
|
tangxifan
|
717906ea17
|
[core] code format
|
2023-08-25 15:13:39 -07:00 |
|
tangxifan
|
89b392a51f
|
[core] adapt changes in is_sb_exist()
|
2023-08-25 15:13:00 -07:00 |