tangxifan
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d1e951e52e
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[test] debugging
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2023-01-24 17:57:34 -08:00 |
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tangxifan
|
f964c9ed67
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[test] debug
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2023-01-24 15:48:57 -08:00 |
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tangxifan
|
8174f53796
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[test] deploy new test to fpga bitstream regression
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2023-01-24 15:42:01 -08:00 |
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tangxifan
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fec84d76d1
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[arch] adding tech lib;
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2023-01-24 15:22:34 -08:00 |
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tangxifan
|
d60d0540da
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[test] adding a new test case to validate the bitstream overloading for DSP blocks
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2023-01-24 14:58:52 -08:00 |
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tangxifan
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f586229b97
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[test] enable rst_on_lut benchmark
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2023-01-18 19:45:41 -08:00 |
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tangxifan
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b7a66705e0
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[test] now use yosys_vpr flow; add rst_on_lut benchmark
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2023-01-18 19:42:50 -08:00 |
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tangxifan
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e974e5ddf7
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[test] now allow to select vpr device layout for test cases that ignores global nets on regular CLB inputs
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2023-01-18 18:31:36 -08:00 |
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tangxifan
|
03273371c0
|
[test] add a new test to validate local reset
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2023-01-18 18:17:14 -08:00 |
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tangxifan
|
2c9593c1d4
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[test] now use a new benchmark: discrete dffn to validate the clk gen locally feature
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2023-01-15 13:09:40 -08:00 |
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tangxifan
|
13aed6fff5
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[test] still commment verification out
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2023-01-15 12:17:59 -08:00 |
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tangxifan
|
758cc7a089
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[test] debugging
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2023-01-15 11:44:48 -08:00 |
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tangxifan
|
14bb76ec87
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[test] remove verification steps for new test but leave a todo
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2023-01-14 23:06:54 -08:00 |
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tangxifan
|
9222d085cd
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[test] now use local clock as one of the pins in a clock bus, but connected to global routing
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2023-01-13 22:04:56 -08:00 |
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tangxifan
|
26f71656de
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[test] update pin constraints
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2023-01-13 21:12:18 -08:00 |
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tangxifan
|
93107c752a
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[test] updating test case
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2023-01-13 19:53:15 -08:00 |
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tangxifan
|
1353577351
|
[test] added a new test to validate locally generated clocks
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2023-01-13 16:45:30 -08:00 |
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tangxifan
|
c7dc3ce7dc
|
[test] pass
|
2023-01-11 17:10:29 -08:00 |
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tangxifan
|
f6f153ace4
|
[test] debugging
|
2023-01-11 17:06:31 -08:00 |
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tangxifan
|
d5ebbeea9a
|
[test] adding a new test to show how to automate generation of bus group files
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2023-01-11 16:59:54 -08:00 |
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tangxifan
|
83d7ff56e1
|
[script] add dedicated testcase for source commands
|
2023-01-01 17:04:24 -08:00 |
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tangxifan
|
d7a95a8ec2
|
[script] fixed some bugs
|
2022-12-30 18:30:52 -08:00 |
|
tangxifan
|
56a3e6e463
|
[test] reduce test size
|
2022-12-30 18:28:17 -08:00 |
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tangxifan
|
ae11a4fbf2
|
[test] add a new test case
|
2022-12-30 18:25:15 -08:00 |
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tangxifan
|
12d114bbae
|
[test] hit the bug of tileable rr_graph skip it
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2022-11-05 10:52:04 -07:00 |
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tangxifan
|
dc24e41c6b
|
[test] relax minW for counter128, as VPR's router degrades in routability
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2022-11-03 19:48:13 -07:00 |
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tangxifan
|
513f7800aa
|
[test] update golden outputs for no_cout_in_gsb testcase
|
2022-11-03 17:51:51 -07:00 |
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tangxifan
|
a88bc2d4de
|
[test] update golden outputs for device4x4
|
2022-11-03 17:51:08 -07:00 |
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tangxifan
|
5f74367c2e
|
[test] update golden for device1x1 no time stamp netlists
|
2022-11-03 17:48:40 -07:00 |
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tangxifan
|
40f1f2fbc6
|
[test] update golden results for iwls
|
2022-10-21 20:28:10 -07:00 |
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tangxifan
|
04286508c8
|
[test] comment out fpu in iwls2005 due to yosys cannot synthesis; bring des back
|
2022-10-21 20:26:56 -07:00 |
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tangxifan
|
00a485cbeb
|
[test] add missing file
|
2022-10-17 19:44:25 -07:00 |
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tangxifan
|
609e096b1a
|
[test] added a new test to validate explicit port direction in pin table support
|
2022-10-17 15:25:19 -07:00 |
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tangxifan
|
8b00bfdff9
|
[test] replace hardcoded paths in task config files with relative paths
|
2022-10-17 11:55:57 -07:00 |
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tangxifan
|
aa78981e37
|
[test] add a new test case 'empty_pcf' to ensure 'free pin assignment' support in pcf2place; Move all the tests related to I/O constraints to a dedicated directory
|
2022-10-17 11:18:21 -07:00 |
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tangxifan
|
b0be27b384
|
[test] add repack design constraints files
|
2022-10-13 11:22:48 -07:00 |
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tangxifan
|
7f67794787
|
[arch]add new arch to test
|
2022-10-13 10:54:40 -07:00 |
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tangxifan
|
ab53f88c2b
|
[test] now use a fixed device layout for the single-mode LUT design testcase
|
2022-10-04 10:05:22 -07:00 |
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tangxifan
|
4eaecde0b9
|
[test] add golden netlists to ensure no cout in gsb
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2022-10-01 11:03:13 -07:00 |
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tangxifan
|
78f30cf072
|
[test] add a new test to track the golden netlists where cout is not in GSB
|
2022-09-30 15:38:27 -07:00 |
|
tangxifan
|
0565ca7aca
|
[script] add missing files
|
2022-09-29 16:14:38 -07:00 |
|
tangxifan
|
a3e7133d63
|
Merge branch 'master' into wire_lut_test
|
2022-09-29 16:02:18 -07:00 |
|
tangxifan
|
ce0fbe1765
|
[test] fixed a few bugs
|
2022-09-29 15:32:31 -07:00 |
|
tangxifan
|
9bc9b61d35
|
[test] fixed a few bugs
|
2022-09-29 15:11:30 -07:00 |
|
tangxifan
|
f5e7ec4dd1
|
[test] add a new test case to validate wire lut case
|
2022-09-29 14:28:59 -07:00 |
|
tangxifan
|
3f8e2ade2e
|
[script] update missing scripts required by pb_pin_fixup test cases
|
2022-09-29 13:39:46 -07:00 |
|
tangxifan
|
49fa783914
|
[script] now suggest to skip pb_pin_fixup step in example scripts for most test cases
|
2022-09-29 10:45:27 -07:00 |
|
tangxifan
|
79b260f5e1
|
[arch] update missing arch
|
2022-09-21 16:52:32 -07:00 |
|
tangxifan
|
b1f8cdab3c
|
[test] update missing arch files which are not placed in the openfpga_flow/vpr_arch
|
2022-09-21 15:28:56 -07:00 |
|
tangxifan
|
b532bca9d2
|
[script] update golden outputs: see no changes in fabric netlists; accept changes in testbenches and bitstreams which comes from the random pin assignment
|
2022-09-21 10:54:16 -07:00 |