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OpenFPGA
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377 Commits

Author SHA1 Message Date
tangxifan f70cc32824 [core] developing checkers for configuration protocol w.r.t. the programming clocks 2023-04-22 08:46:36 +08:00
tangxifan 50e201feeb [core] now clock routing for programmable clock network works for 1 clock design 2023-03-07 13:13:25 -08:00
tangxifan 2ff3ad61ce [core] format 2023-03-06 21:57:44 -08:00
tangxifan 45107bf14f [core] debugging 2023-03-06 21:48:19 -08:00
tangxifan 6f2572324e [core] developing route clock rr_graph command 2023-02-28 11:52:38 -08:00
tangxifan b3dec93eb9 [core] code format 2023-02-27 15:12:59 -08:00
tangxifan b6eace8fac [core] now switch id is linked in clock network 2023-02-27 13:10:54 -08:00
tangxifan 009d711ba5 [core] code format 2023-02-26 22:23:41 -08:00
tangxifan 87a9146082 [core] adding rr spatial lookup for clock nodes only 2023-02-26 22:23:17 -08:00
tangxifan 780fc0f26d [core] developing validators and annotate rr_segment for clock arch 2023-02-26 18:03:55 -08:00
tangxifan 7f07a9d031 [lib] add default seg/switch to clock arch. Fixed syntax 2023-02-24 19:15:39 -08:00
tangxifan ee0459d729 [core] developing append_clock_rr_graph function 2023-02-24 17:58:37 -08:00
tangxifan aa55c692d7 [core] starting developing core function for clock rr_graph build-up 2023-02-23 18:04:07 -08:00
tangxifan 786b458a27 [core] adding new command 'append_clock_rr_graph' 2023-02-23 13:30:18 -08:00
tangxifan b78ca69fe5 [core] enable clock arch link 2023-02-22 22:29:16 -08:00
tangxifan e1dab3d227 [code] format 2023-02-22 22:01:24 -08:00
tangxifan e175472a07 [core] adding new commands 2023-02-22 21:58:25 -08:00
tangxifan f00acf1e62 [code] fixed all the compiler warnings under openfpga/src 2023-01-31 12:51:52 -08:00
tangxifan c55d54d325 [code] format 2023-01-11 17:19:04 -08:00
tangxifan c00c43cbd4 [core] fixed a few bugs 2023-01-11 16:39:25 -08:00
tangxifan 9bbb09ef0f [core] adding a new command 'exec_external' to run system call 2023-01-11 16:31:26 -08:00
tangxifan b569d6b603 [core] format 2023-01-07 11:40:17 -08:00
tangxifan c7a4d25e35 [core] now all the commands can be optionally hidden 2023-01-07 11:36:10 -08:00
tangxifan 4385b364af [code] now setup command can be hidden optionally 2023-01-07 11:18:43 -08:00
tangxifan 52e803804d [core] add missing file 2023-01-06 22:37:55 -08:00
tangxifan 2fc047daff [core] format 2023-01-06 21:11:12 -08:00
tangxifan cf824e7161 [core] now bitstream commands follow templates 2023-01-06 21:08:50 -08:00
tangxifan 26c294679a [core] now setup commands follow templates 2023-01-06 20:52:37 -08:00
tangxifan a99794f51c [core] now FPGA-SDC commands follow templates 2023-01-06 19:22:51 -08:00
tangxifan 401b640852 [core] format 2023-01-06 17:50:47 -08:00
tangxifan 12134f4106 [core] now openfpga verilog commands follow templates 2023-01-06 17:48:00 -08:00
tangxifan 93c00207ab [core] now command functions are templates, which can be used by other extensions 2023-01-06 17:23:01 -08:00
tangxifan 5606566839 [engine] format 2023-01-01 17:37:44 -08:00
tangxifan 7610e536bf [engine] now 'source' command can be seen in help desk 2023-01-01 12:01:37 -08:00
tangxifan 76570e653c [engine] format 2023-01-01 10:23:18 -08:00
tangxifan c90f8389f1 [engine] debugged 2023-01-01 10:22:47 -08:00
tangxifan 8d947c7bdb [engine] now developers can write their superset command based on other commands through openfpga shell 2023-01-01 10:10:09 -08:00
tangxifan f1a317b384 [engine] format 2022-11-24 21:04:04 -08:00
tangxifan 24a174c7a4 [engine] fixed syntax errors 2022-11-23 17:06:27 -08:00
tangxifan 07424b1e7f [engine] now main() is encapuslated in a class OpenfpgaShell 2022-11-23 16:52:22 -08:00
tangxifan c4de6655b6 [engine] bug 2022-10-17 15:26:21 -07:00
tangxifan 0f2b8da7f0 [engine] code format 2022-10-17 14:55:34 -07:00
tangxifan 63d8b00630 [engine] syntax 2022-10-17 14:54:18 -07:00
tangxifan 11624cd0c6 [engine] enabling new feature: pin_table_direction_convention 2022-10-17 14:08:21 -07:00
tangxifan 6d31b319a2 [engine] update source files subject to code formatting rules 2022-10-06 17:08:50 -07:00
tangxifan fb2693171b [engine] fixed a bug which causes errors in repacker 2022-09-28 16:30:11 -07:00
tangxifan 36b3e64b35 [engine] now pb_fixup can also accept vtr's post-routing-clustering sync up results 2022-09-28 12:17:16 -07:00
tangxifan 3285af4107 [engine] syntax 2022-09-28 11:39:37 -07:00
tangxifan 51f54bbf20 [engine] developing the steps to annotate clustering results 2022-09-27 16:54:48 -07:00
tangxifan 3c6ef1925c [engine] now sort ipin incoming edges 2022-09-19 11:00:08 -07:00
tangxifan 373566416c Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-16 16:47:21 -07:00
tangxifan 2fc124e109 [engine] now repack has a new option "--ignore_global_nets_on_pins" 2022-09-12 16:18:26 -07:00
tangxifan 56619f9a47 Merge branch 'master' of https://github.com/lnis-uofu/OpenFPGA into vtr_upgrade 2022-09-07 15:04:05 -07:00
tangxifan eab3580f79 [engine] now consider circuit model rather than switchId and SegmentId when identifying GSB structure similarity 2022-09-06 13:40:29 -07:00
tangxifan 71ad0721a1
Merge branch 'master' into vtr_upgrade 2022-08-31 13:56:17 -07:00
tangxifan 3656154913 [engine] fixed syntax errors 2022-08-29 21:17:48 -07:00
tangxifan 12a30196e0 [engine] updating gsb writer; Unfinished!!! 2022-08-29 16:58:48 -07:00
tangxifan ba6ae05091 [engine] update vtr and add in_edge checks to link_arch 2022-08-24 12:22:20 -07:00
tangxifan 5d6a90d983 [engine] remove compile warnings 2022-08-22 20:59:50 -07:00
tangxifan 800ce6a290 [engine] avoid function naming conflicts 2022-08-18 19:33:56 -07:00
tangxifan e9c4d102c1 [engine] rename files to avoid conflicts with VPR files 2022-08-17 20:01:50 -07:00
tangxifan 8f1aac885e [engine] fixing mismatches in APIs 2022-08-17 14:19:02 -07:00
tangxifan 4e871be357 [engine] adapt the use of API in RRGraph for annotation functions 2022-08-17 10:50:16 -07:00
tangxifan 0c329866da [engine] Use RRGraphView in openfpga source codes 2022-08-16 16:48:32 -07:00
tangxifan c1256ae818 [engine] added command 'pcf2place' to openfpga 2022-07-28 11:30:36 -07:00
tangxifan 2a5bffa6b9 [engine] developing pcf2place integration to openfpga 2022-07-28 10:30:43 -07:00
tangxifan 1c9da96f59 [lib] move io_location_map to libpcf 2022-07-26 16:00:28 -07:00
tangxifan 23f98d6a3b [engine] fixed a few bugs 2022-07-26 13:55:29 -07:00
tangxifan 85bcb36f34 [engine] fix compiler errors 2022-07-26 12:25:40 -07:00
tangxifan 0862eceed0 [engine] add an XML write to io location map: In the long run, we should decouple the writer function from the data structure!!! 2022-07-26 12:17:45 -07:00
taoli4rs 3762a3aae4 Code clean up based on review. 2022-07-20 14:34:44 -07:00
taoli4rs cfc0d08060 Add constrain_pin_location command in openfpga; add full flow test. 2022-07-20 11:51:00 -07:00
tangxifan 755be78b39 [Engine] Now GSB output file contains segments name and pin name in SB module 2022-04-10 21:22:30 +08:00
tangxifan 6171abdf95 [FPGA-Bitstream] Now report_bitstream_distribution includes fabric bitstream stats 2022-03-29 19:41:15 +08:00
tangxifan 6da0ede9b0 [FPGA-Verilog] Adding bus group support to all Verilog testbench generators 2022-02-17 23:48:44 -08:00
tangxifan c96f0d199d [FPGA-Verilog] Adding bus group support in Verilog testbenches 2022-02-17 23:14:28 -08:00
tangxifan 1c94d0f285 [FPGA-Verilog] Now preconfig testbench generator has a new option ``--use_relative_path`` 2022-02-01 13:25:09 -08:00
tangxifan f311a034bb [FPGA-Verilog] Now full testbench generator has a new option ``--use_relative_path`` 2022-02-01 12:17:02 -08:00
tangxifan 63f44adf15 [FPGA-Verilog] Now have a new option ``--use_relative_path`` 2022-01-31 12:48:05 -08:00
tangxifan a9a56686e2 [Engine] Add a new option ``--unique`` to command ``write_gsb_to_xml`` 2022-01-26 11:10:29 -08:00
tangxifan 33064ca4cf [FPGA-SDC] Add a new option ``--no_time_stamp`` to all the commands 2022-01-25 15:51:28 -08:00
tangxifan b09e13b42c [FPGA-Verilog] Fixed a bug on invalid option of a command 2022-01-25 13:45:44 -08:00
tangxifan 25143d07f1 [FPGA-Bitstream] Now has a new option ``--no_time_stamp`` to all the commands that output bitstream files 2022-01-25 13:37:54 -08:00
tangxifan 62b57b05d2 [Engine] Now FPGA-Verilog commands have a new option ``--no_time_stamp`` 2022-01-25 12:09:08 -08:00
tangxifan 6586ea7816 [Engine] Bug fix for fabric key writer which errors out when there is no BL/WL banks in the architecture 2021-10-11 09:40:02 -07:00
tangxifan b9c540ec3f [Engine] Upgrade fabric key writer to support BL/WL shift register banks 2021-10-10 21:14:14 -07:00
tangxifan 34575f7222 [FPGA-Bitstream] Upgrade bitstream generator to support multiple shift register banks in a configuration region for QuickLogic memory bank 2021-10-09 20:39:45 -07:00
tangxifan 8f5f30792f [Engine] Now the MemoryBankShiftRegisterBanks data structure combines both BL/WL data structures as the unified interface 2021-10-08 15:25:37 -07:00
tangxifan 2ea9826b17 [FPGA-Bitstream] Bug fix in wrong option name 2021-10-05 18:58:47 -07:00
tangxifan ad54c8547e [FPGA-Bitstream] Added an option to ``write_fabric_bitstream`` command to enable outputting don't care bits in bitstream files 2021-10-05 18:54:02 -07:00
tangxifan 977d81679d [Engine] Upgrade check codes for WL CCFF 2021-10-01 17:23:10 -07:00
tangxifan 2d4c200d58 [FPGA-Verilog] Now FPGA-Verilog can output shift register bank netlists 2021-09-29 20:56:02 -07:00
tangxifan b87b7a99c5 [Engine] Add MemoryBankShiftRegisterBanks to openfpga context because their contents are required by netlist writers as well as bitstream generators 2021-09-29 20:21:46 -07:00
tangxifan 7723e00e6c [Engine] Adding the function that builds a shift register module for BL/WLs 2021-09-28 22:49:24 -07:00
tangxifan 2de4a460a8 [Engine] Rework the function that counts the number of configurable children for fabric key writer and bitstream generator 2021-09-24 15:15:32 -07:00
tangxifan 18257b3fa1 [Engine] Update BL/WL port addition for the top-level module in fabric generator 2021-09-24 11:07:58 -07:00
tangxifan 8c281a22b0 [Engine] Add check codes to validate circuit models for BL/WL protocols 2021-09-23 14:39:16 -07:00
tangxifan 962acda810 [Engine] Bug fix in fabric key generation when computing configurable children 2021-09-22 11:09:46 -07:00
tangxifan 36a4da863c [Engine] Support WLR port in OpenFPGA architecture file and fabric generator 2021-09-20 16:05:36 -07:00
tangxifan b787c4e100 [Engine] Register QL memory bank as a legal protocol 2021-09-09 15:06:51 -07:00