tangxifan
|
5618f1d567
|
[core] now bitgen uses config child types
|
2023-08-03 16:06:19 -07:00 |
|
tangxifan
|
3331540ed6
|
[core] using config child type in bitstream generation
|
2023-08-03 14:24:22 -07:00 |
|
tangxifan
|
2facde2097
|
[core] reworked fabric generator to use config child type
|
2023-08-03 12:57:50 -07:00 |
|
tangxifan
|
5895a1d96b
|
[core] reworking fabric generator based on latest changes on configurable children
|
2023-08-02 22:50:19 -07:00 |
|
tangxifan
|
27cae41123
|
[core] rework physical and logical types of configurable child
|
2023-08-02 20:37:27 -07:00 |
|
tangxifan
|
87f2822ef8
|
[core] working on logical and physical children
|
2023-08-02 19:46:27 -07:00 |
|
tangxifan
|
c05f12ac11
|
[core] sync up logical-to-physical configurable child mapping after physical memory build-up
|
2023-08-02 12:24:16 -07:00 |
|
tangxifan
|
470ab84489
|
[core] developing group config block support for routing module
|
2023-08-01 22:57:22 -07:00 |
|
tangxifan
|
53050b94ab
|
[core] developing memory group modules in grid modules
|
2023-08-01 17:50:03 -07:00 |
chungshien
|
eed96b395e
|
Misc - update comment + remove code that not being used
|
2023-08-01 07:33:17 -07:00 |
|
tangxifan
|
23643f3fb1
|
[core] developing the physical memory block builder
|
2023-07-31 22:57:26 -07:00 |
|
tangxifan
|
2d2b8f67aa
|
[core] adding new option '--group_config_block' to command 'build_fabric'
|
2023-07-31 17:32:48 -07:00 |
chungshien
|
c1b5ca0941
|
Merge branch 'master' into openfpga-issue-1256
|
2023-07-31 01:18:10 -07:00 |
|
cschai
|
aae037bf77
|
Address comment
|
2023-07-30 02:18:48 -07:00 |
|
cschai
|
838cf0d818
|
Address comment
|
2023-07-30 01:14:11 -07:00 |
|
cschai
|
56d76741d5
|
Address comment
|
2023-07-30 00:39:16 -07:00 |
|
cschai
|
63459218e5
|
Address comment
|
2023-07-30 00:24:40 -07:00 |
|
tangxifan
|
beaa687a20
|
[core] fixed bugs on supporting heterogeneous blocks in tile modules
|
2023-07-27 20:29:18 -07:00 |
|
tangxifan
|
c2066cc63c
|
[core] fixed a bug where pb/cb/sb instance name is not assigned correctly in bitstream manager under tile modules
|
2023-07-27 13:33:23 -07:00 |
|
tangxifan
|
156cb800aa
|
[core] fixed a critical bug which causes wrong connections in tile modules
|
2023-07-27 12:22:16 -07:00 |
|
tangxifan
|
dd486f5ccb
|
[core] fixed a bug on checking if cb is in a tile
|
2023-07-27 11:14:05 -07:00 |
|
tangxifan
|
cfec6c88f1
|
[core] fixed a bug in cb instance naming
|
2023-07-27 10:59:46 -07:00 |
|
tangxifan
|
be0715a81c
|
[core] fixed a bug on cb instance name. Spot some bug in port naming for tile modules
|
2023-07-27 10:42:56 -07:00 |
|
tangxifan
|
97219fd825
|
[core] add more verbose to help debug failed test cases
|
2023-07-26 23:26:11 -07:00 |
|
tangxifan
|
19ed9ea669
|
Merge branch 'master' into openfpga-issue-1256
|
2023-07-26 10:32:30 -07:00 |
|
tangxifan
|
f5e8f175fb
|
[core] fixed a bug which causes flow failures when group_tile is not enabled
|
2023-07-25 21:27:58 -07:00 |
|
tangxifan
|
83428a209e
|
[core] fixed a bug on io indexing which causes tile-based test cases failed in dv
|
2023-07-25 16:03:50 -07:00 |
|
tangxifan
|
de6956530f
|
[core] disable pnr sdc for tile-based fabric
|
2023-07-25 15:38:41 -07:00 |
|
tangxifan
|
6ecbbb3a94
|
[core] fixed a bug in fabric bitgen due to tile modules
|
2023-07-25 14:49:12 -07:00 |
|
tangxifan
|
95a32628ab
|
[core] fixed the bug in arch bitgen due to the tile modules
|
2023-07-25 14:15:15 -07:00 |
|
tangxifan
|
64698443c9
|
[core] fixed a bug on io location map for tile modules
|
2023-07-24 22:11:57 -07:00 |
|
tangxifan
|
2105abdbca
|
[core] fixed a bug
|
2023-07-24 21:26:29 -07:00 |
|
tangxifan
|
e7d714b94d
|
[core] fixed a bug on the tile module port addition: some grid output was not pulled out
|
2023-07-24 21:21:25 -07:00 |
|
tangxifan
|
b8d080b08e
|
[core] fixed a bug where undriven cb ports are not connected to tile
|
2023-07-24 20:40:25 -07:00 |
|
tangxifan
|
3745897ff6
|
[core] fixed a few bugs
|
2023-07-24 16:10:29 -07:00 |
|
tangxifan
|
48b0ba8b78
|
[core] format
|
2023-07-24 15:00:26 -07:00 |
|
tangxifan
|
4294914987
|
[core] fixed compiler warnings
|
2023-07-24 14:59:43 -07:00 |
|
tangxifan
|
812473ef04
|
[core] fixed the bug on io location map for tiled top module
|
2023-07-24 14:50:39 -07:00 |
|
tangxifan
|
da36b735c6
|
[core] syntax
|
2023-07-24 12:13:45 -07:00 |
|
tangxifan
|
f031148959
|
[core] syntax
|
2023-07-23 22:39:36 -07:00 |
|
tangxifan
|
f551188d0f
|
[core] developed tile directs to support tile modules
|
2023-07-23 21:45:45 -07:00 |
|
tangxifan
|
14666f3ae5
|
[core] sync
|
2023-07-23 20:45:59 -07:00 |
|
tangxifan
|
0b3b7b5472
|
[core] hotfix
|
2023-07-23 13:39:06 -07:00 |
|
tangxifan
|
1ee7448070
|
[core] supporting tile annotation (for global port) in tile modules
|
2023-07-23 13:38:16 -07:00 |
|
tangxifan
|
399259ea1d
|
[core] adding prog clock arch support for tile modules
|
2023-07-23 13:11:13 -07:00 |
|
tangxifan
|
0f3f4b0d81
|
[core] now tile module use unique port name (for heterogeneous blocks)
|
2023-07-22 23:55:54 -07:00 |
|
tangxifan
|
003d9515ff
|
[core] developing tile-based top module builder
|
2023-07-22 17:13:30 -07:00 |
|
tangxifan
|
93c5a68592
|
[core] developing top-level nets for tiles
|
2023-07-21 23:21:53 -07:00 |
|
Chung Shien Chai
|
6c03819c5f
|
100% limited new flow for flatten bl/wl protocol
|
2023-07-21 03:14:26 -07:00 |
|
tangxifan
|
fcf308fcd6
|
[core] developing inter-tile connections for top module
|
2023-07-20 23:00:35 -07:00 |
|
Chung Shien Chai
|
39934f9d16
|
Address issue 1256
|
2023-07-20 22:34:18 -07:00 |
|
tangxifan
|
b70f7fb1b6
|
[core] now option conflicts in command 'build_fabric' can error out
|
2023-07-20 21:22:07 -07:00 |
|
tangxifan
|
6b92299e39
|
[core] start working on the net build-up for tile instances under the top-level module
|
2023-07-20 17:38:13 -07:00 |
|
tangxifan
|
88c5d122ca
|
[core] syntax
|
2023-07-20 17:12:10 -07:00 |
|
tangxifan
|
db179ec4bb
|
[core] split tile instance builder and the classic fine-grained builder
|
2023-07-20 17:07:07 -07:00 |
|
tangxifan
|
ef214f4590
|
[core] code format
|
2023-07-20 17:00:29 -07:00 |
|
tangxifan
|
6458580e3e
|
[core] move child instance builder to a separated source file as these codes are expanding in size
|
2023-07-20 16:59:39 -07:00 |
|
tangxifan
|
bd265334b5
|
[core] added tile instances to top module builder
|
2023-07-19 23:26:55 -07:00 |
|
tangxifan
|
a06b9a0f48
|
[core] now start to develop the tile instances under the top module
|
2023-07-19 22:22:07 -07:00 |
|
tangxifan
|
2e69eebea0
|
[core] now tile module builder is working
|
2023-07-19 17:23:44 -07:00 |
|
tangxifan
|
0d03d7b483
|
[core] now fabric tile cache both grid and gsb coord for pb
|
2023-07-19 17:20:53 -07:00 |
|
tangxifan
|
778d03610c
|
[core] debugging
|
2023-07-19 15:27:05 -07:00 |
|
tangxifan
|
001b3b3f8b
|
[core] debugging
|
2023-07-19 14:38:07 -07:00 |
|
tangxifan
|
d03fa92ddf
|
[core] debugging
|
2023-07-19 12:49:35 -07:00 |
|
tangxifan
|
48e207d3e4
|
[core] debugging
|
2023-07-19 12:22:57 -07:00 |
|
tangxifan
|
6607bb7e48
|
[core] now fpga verilog supports tile modules
|
2023-07-18 22:35:22 -07:00 |
|
tangxifan
|
5ae146bd86
|
[core] finish up tile module builder
|
2023-07-18 21:17:40 -07:00 |
|
tangxifan
|
0dcec9d8e5
|
[core] finishing up tile module builder
|
2023-07-18 17:56:27 -07:00 |
|
tangxifan
|
403ed4ea60
|
[core] still developing tile module port and net builder
|
2023-07-18 16:03:47 -07:00 |
|
tangxifan
|
aabcc25567
|
[core] developing tile module port and net builder
|
2023-07-17 23:06:55 -07:00 |
|
tangxifan
|
ba4b7e3522
|
[core] developing tile module builder
|
2023-07-16 15:18:09 -07:00 |
|
tangxifan
|
98c598cec2
|
[core] unique tile identifier done
|
2023-07-15 22:54:33 -07:00 |
|
tangxifan
|
ea8d128789
|
[core] syntax
|
2023-07-15 20:29:21 -07:00 |
|
tangxifan
|
c2ef5ca408
|
[core] developing top-left style tile info
|
2023-07-14 22:48:44 -07:00 |
|
tangxifan
|
091ac88c7e
|
[lib] code format
|
2023-07-14 12:16:40 -07:00 |
|
tangxifan
|
3bc959dcec
|
[lib] create tile config lib and start integration to core
|
2023-07-14 12:13:31 -07:00 |
|
tangxifan
|
c58035dbd4
|
[core] start developing option --group_tile for build_fabric
|
2023-07-14 11:01:04 -07:00 |
|
tangxifan
|
3de4d3fc09
|
[core] add a new command 'write_fabric_key' and now writer supports module-level keys
|
2023-07-08 18:12:51 -07:00 |
|
tangxifan
|
433391eec4
|
[core] move new functions to a separated source file
|
2023-07-07 15:03:03 -07:00 |
|
tangxifan
|
d3aa4c53d0
|
[core] now support rebuild configuarable children for ccff submodules
|
2023-07-07 14:51:21 -07:00 |
|
tangxifan
|
a1b13b8e12
|
[core] overload submodule configurable children from fabric key
|
2023-07-06 22:47:57 -07:00 |
|
tangxifan
|
d3109ee88b
|
[core] developing configurable children reloading from fabric key
|
2023-07-06 21:53:22 -07:00 |
|
tangxifan
|
ddfb0c4afd
|
[core] now mock fpga top supports fpga core wrapper
|
2023-06-26 15:06:11 -07:00 |
|
tangxifan
|
83fa6a421e
|
[core] code format
|
2023-06-26 10:06:17 -07:00 |
|
tangxifan
|
70f40cd21a
|
[core] fixing bugs in the preconfig module when supporting dut module of fpga_core
|
2023-06-26 10:03:19 -07:00 |
|
tangxifan
|
919d6d8608
|
[test] added more testcases to validate the dut module option; fixing bugs on preconfigured testbenches
|
2023-06-25 22:49:51 -07:00 |
|
tangxifan
|
205881d0e7
|
[core] fixed the bug when using fpga_core instead of fpga_top
|
2023-06-25 18:03:15 -07:00 |
|
tangxifan
|
150653287d
|
[core] supporting io naming for verilog testbench generators
|
2023-06-25 15:29:27 -07:00 |
|
tangxifan
|
987a562e0f
|
[core] fixed the bug when checking mapping status of fpga core ports
|
2023-06-23 17:21:52 -07:00 |
|
tangxifan
|
463332c77a
|
[core] code complete for adding nets between top and core module
|
2023-06-23 13:21:25 -07:00 |
|
tangxifan
|
b30148f8fb
|
[core] apply more sanity checks on top module port
|
2023-06-23 12:37:46 -07:00 |
|
tangxifan
|
2484150ab6
|
[core] working on port addition to top module
|
2023-06-23 12:21:47 -07:00 |
|
tangxifan
|
8bd9ae02fd
|
[core] io name map now supports dummy port direction
|
2023-06-23 11:09:33 -07:00 |
|
tangxifan
|
7961223eac
|
[core] enabling io naming rules in fabric builder
|
2023-06-22 22:18:09 -07:00 |
|
tangxifan
|
61544af2b4
|
[core] start adding new options
|
2023-06-21 14:01:00 -07:00 |
|
tangxifan
|
b2d1d1b6bd
|
[core] fixed a bug on fpga bitstream when supporting fpga_core
|
2023-06-19 14:40:38 -07:00 |
|
tangxifan
|
299b42873d
|
[core] fix no warning build
|
2023-06-19 13:01:43 -07:00 |
|
tangxifan
|
a4f26798b0
|
[core] fixed the bug which causes wrong fpga top connections and failed in fpga sdc
|
2023-06-19 11:59:48 -07:00 |
|
tangxifan
|
63ee0c980e
|
[core] fixed some bugs
|
2023-06-18 22:12:54 -07:00 |
|
tangxifan
|
d9499f2b40
|
[core] now fpga bitstream supports the wrapper module
|
2023-06-18 21:58:36 -07:00 |