tangxifan
|
2fbb88d25b
|
remove legacy codes
|
2019-11-05 13:52:42 -07:00 |
|
tangxifan
|
66047e4a45
|
refactoring Verilog simulation flag generations
|
2019-11-05 13:45:11 -07:00 |
|
tangxifan
|
13f2d33d37
|
refactored fpga_define.v generation
Please enter the commit message for your changes. Lines starting
|
2019-11-05 12:41:43 -07:00 |
|
tangxifan
|
8ef9e994d8
|
rename source files to be what they are actually doing
|
2019-11-05 12:18:23 -07:00 |
|
tangxifan
|
aaaf7a0d19
|
remove legacy codes in writing include netlists
|
2019-11-04 21:06:14 -07:00 |
|
tangxifan
|
ebab0e91ef
|
refactored include netlist writer
|
2019-11-04 20:55:30 -07:00 |
|
tangxifan
|
5d507ae8ee
|
bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!!
|
2019-11-04 18:05:50 -07:00 |
|
tangxifan
|
69bc858e62
|
bring autocheck top testbench back to simulation deck, start testing
|
2019-11-04 15:35:04 -07:00 |
|
tangxifan
|
3274a49779
|
fine tuning top testbench and getting ready for testing
|
2019-11-04 12:08:36 -07:00 |
|
tangxifan
|
d7bbae76a4
|
adding stimuli to benchmark inputs in top-level testbench
|
2019-11-03 20:20:14 -07:00 |
|
tangxifan
|
3e9968d2f0
|
keep refactoring top-level testbench with auto-check features
|
2019-11-03 18:59:54 -07:00 |
|
tangxifan
|
1fb29df1e2
|
cleaning verilog file lines
|
2019-11-03 17:58:18 -07:00 |
|
tangxifan
|
0ec465d4e1
|
refactoring auto-check top Verilog testbench
|
2019-11-03 17:41:29 -07:00 |
|
tangxifan
|
dc241e6c03
|
add explicit port mapping support in testbenches; remove dangling ports in benchmarks
|
2019-11-02 23:03:47 -06:00 |
|
tangxifan
|
05a830de1b
|
bring ini writer for formality scripts back
|
2019-11-02 18:56:54 -06:00 |
|
tangxifan
|
c681726124
|
try to enlarge write buffers in ini writer, but these codes should be fully reworked
|
2019-11-02 18:33:05 -06:00 |
|
tangxifan
|
3ad2a93539
|
start bring back ini writer bit by bit
|
2019-11-02 18:20:25 -06:00 |
|
tangxifan
|
cb74d120e7
|
shadow ini writer to help debugging
|
2019-11-02 17:31:05 -06:00 |
|
tangxifan
|
fc164abd49
|
remove unused variable in sim info writer
|
2019-11-02 16:35:32 -06:00 |
|
tangxifan
|
e1a7a2895a
|
simulation ini file name can be customizable
|
2019-11-02 09:59:34 -06:00 |
|
tangxifan
|
d5d7450ce7
|
make simulation ini writing as an option
|
2019-11-02 09:46:12 -06:00 |
|
tangxifan
|
c3db880599
|
adding explicit file path to simulation info writer
|
2019-11-02 09:21:02 -06:00 |
|
tangxifan
|
358e9892ac
|
reduce some error message to warnings
|
2019-11-02 00:09:13 -06:00 |
|
tangxifan
|
f70f387f9f
|
minor tuning on ini compilation
|
2019-11-01 20:51:49 -06:00 |
|
tangxifan
|
3669a47d3b
|
reworked the ini writer
|
2019-11-01 20:25:01 -06:00 |
|
tangxifan
|
dab66b8be7
|
start adding auto check cpp files
|
2019-11-01 19:49:50 -06:00 |
|
tangxifan
|
e2b042c61c
|
Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring
|
2019-11-01 18:27:27 -06:00 |
Ganesh Gore
|
a0512e40b1
|
Created intermidiate file for modelsim simulation
|
2019-11-01 18:20:00 -06:00 |
|
tangxifan
|
3ae841b80f
|
start refactoring auto-check top testbench generation
|
2019-11-01 16:33:12 -06:00 |
|
tangxifan
|
531cc064fc
|
bug fixing for formal top-level testbench
|
2019-11-01 10:47:40 -06:00 |
|
Ganesh Gore
|
da0778e813
|
Merge remote-tracking branch 'lnis_origin/refactoring' into ganesh_dev
|
2019-11-01 00:46:34 -06:00 |
|
tangxifan
|
2dff779005
|
critical bug fixed for bitstream generation for offset truth tables
|
2019-10-31 20:16:08 -06:00 |
|
tangxifan
|
a6a3e7c36b
|
adding mcnc_big20 to regression test
|
2019-10-31 19:31:27 -06:00 |
|
tangxifan
|
858c1aefce
|
try use force for Icarus
|
2019-10-30 19:50:34 -06:00 |
|
tangxifan
|
7460dc8cab
|
pass current regression tests
|
2019-10-30 19:10:36 -06:00 |
|
tangxifan
|
55fbd72293
|
many bugs have been fixed
|
2019-10-30 15:50:42 -06:00 |
|
tangxifan
|
4398cffaaa
|
single mode is working, multi-mode is under debugging
|
2019-10-29 22:32:36 -06:00 |
|
tangxifan
|
1faacfa3cf
|
keep autocheck testbenches underwater now, bring them back when refactored. Start plugging in the new engine
|
2019-10-29 14:23:09 -06:00 |
|
tangxifan
|
7c116aac2f
|
added Verilog generation for preconfig top module
|
2019-10-29 13:54:35 -06:00 |
|
tangxifan
|
10491c4291
|
bring single mode test case online with bug fixing
|
2019-10-28 17:04:10 -06:00 |
|
tangxifan
|
fe005f1f56
|
remove legacy codes for Verilog formal verification testbench generation
|
2019-10-28 15:21:14 -06:00 |
|
tangxifan
|
c047fd3cb2
|
plugged in the refactored formal verification Verilog testbench using random vectors
|
2019-10-28 15:10:29 -06:00 |
|
tangxifan
|
ccabe4ce2a
|
refactoring Verilog formal verification top testbench using random vectors
|
2019-10-28 14:45:51 -06:00 |
|
tangxifan
|
55eea6c4d5
|
rename files to be clear
|
2019-10-27 20:12:48 -06:00 |
|
tangxifan
|
35073f48cf
|
add runtime profiling to module graph builders
|
2019-10-27 19:10:21 -06:00 |
|
tangxifan
|
2b06cfc3cf
|
added fabric bitstream generator and fixed critical bugs in top module graph
|
2019-10-27 18:47:33 -06:00 |
|
tangxifan
|
f116351831
|
add instance name for each pb graph node
|
2019-10-26 17:25:45 -06:00 |
|
tangxifan
|
7649d9228e
|
fixed bugs in refactored bitstream generation
|
2019-10-26 16:40:14 -06:00 |
|
tangxifan
|
0a9c89be0b
|
add bitstream writers and start debugging
|
2019-10-26 12:41:23 -06:00 |
|
tangxifan
|
3310bac65b
|
refactored grid bitstream generation
|
2019-10-25 21:49:47 -06:00 |