Commit Graph

1171 Commits

Author SHA1 Message Date
tangxifan 2fbb88d25b remove legacy codes 2019-11-05 13:52:42 -07:00
tangxifan 66047e4a45 refactoring Verilog simulation flag generations 2019-11-05 13:45:11 -07:00
tangxifan 13f2d33d37 refactored fpga_define.v generation
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2019-11-05 12:41:43 -07:00
tangxifan 8ef9e994d8 rename source files to be what they are actually doing 2019-11-05 12:18:23 -07:00
tangxifan aaaf7a0d19 remove legacy codes in writing include netlists 2019-11-04 21:06:14 -07:00
tangxifan ebab0e91ef refactored include netlist writer 2019-11-04 20:55:30 -07:00
tangxifan 5d507ae8ee bug fixing in memory module generation; some work should be done to merge nets and uniquifying nets!!! 2019-11-04 18:05:50 -07:00
tangxifan 69bc858e62 bring autocheck top testbench back to simulation deck, start testing 2019-11-04 15:35:04 -07:00
tangxifan 3274a49779 fine tuning top testbench and getting ready for testing 2019-11-04 12:08:36 -07:00
tangxifan d7bbae76a4 adding stimuli to benchmark inputs in top-level testbench 2019-11-03 20:20:14 -07:00
tangxifan 3e9968d2f0 keep refactoring top-level testbench with auto-check features 2019-11-03 18:59:54 -07:00
tangxifan 1fb29df1e2 cleaning verilog file lines 2019-11-03 17:58:18 -07:00
tangxifan 0ec465d4e1 refactoring auto-check top Verilog testbench 2019-11-03 17:41:29 -07:00
tangxifan dc241e6c03 add explicit port mapping support in testbenches; remove dangling ports in benchmarks 2019-11-02 23:03:47 -06:00
tangxifan 05a830de1b bring ini writer for formality scripts back 2019-11-02 18:56:54 -06:00
tangxifan c681726124 try to enlarge write buffers in ini writer, but these codes should be fully reworked 2019-11-02 18:33:05 -06:00
tangxifan 3ad2a93539 start bring back ini writer bit by bit 2019-11-02 18:20:25 -06:00
tangxifan 644ca4f0a4 add vpr test run in Travis 2019-11-02 17:49:22 -06:00
tangxifan cb74d120e7 shadow ini writer to help debugging 2019-11-02 17:31:05 -06:00
tangxifan fc164abd49 remove unused variable in sim info writer 2019-11-02 16:35:32 -06:00
tangxifan 0852ef33c3 remove caching for deps 2019-11-02 16:30:01 -06:00
tangxifan e1a7a2895a simulation ini file name can be customizable 2019-11-02 09:59:34 -06:00
tangxifan d5d7450ce7 make simulation ini writing as an option 2019-11-02 09:46:12 -06:00
tangxifan c3db880599 adding explicit file path to simulation info writer 2019-11-02 09:21:02 -06:00
tangxifan 358e9892ac reduce some error message to warnings 2019-11-02 00:09:13 -06:00
tangxifan 5bae8fecde add debugging mode to see why travis failed 2019-11-01 23:26:08 -06:00
tangxifan 495000c649 recover caching for libs 2019-11-01 21:37:17 -06:00
tangxifan 17f816effd try to uncache libini 2019-11-01 21:26:22 -06:00
tangxifan e9ed64c926 try to let cmake identify libini 2019-11-01 21:17:35 -06:00
tangxifan f811ddc62a Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-11-01 20:52:45 -06:00
tangxifan f70f387f9f minor tuning on ini compilation 2019-11-01 20:51:49 -06:00
Ganesh Gore a880802803 Bug Fix: Corrected read VPR stat filename 2019-11-01 20:51:05 -06:00
tangxifan a9c02cd2a5 fix errors in travis 2019-11-01 20:32:40 -06:00
tangxifan 550df19ee2 use a stable cmake now 2019-11-01 20:26:29 -06:00
tangxifan 3669a47d3b reworked the ini writer 2019-11-01 20:25:01 -06:00
tangxifan dab66b8be7 start adding auto check cpp files 2019-11-01 19:49:50 -06:00
tangxifan e2b042c61c Merge branch 'ganesh_dev' of https://github.com/LNIS-Projects/OpenFPGA into refactoring 2019-11-01 18:27:27 -06:00
Ganesh Gore 370a5ed408 Bug Fix: shifter ff.v include path to tcl script 2019-11-01 18:22:40 -06:00
Ganesh Gore 595d2d3070 Simple argument shuffle 2019-11-01 18:21:26 -06:00
Ganesh Gore 27005d6640 Added Modelsim Python Script 2019-11-01 18:20:40 -06:00
Ganesh Gore a0512e40b1 Created intermidiate file for modelsim simulation 2019-11-01 18:20:00 -06:00
tangxifan 4d4ef1113d give up iverilog on travis 2019-11-01 17:53:50 -06:00
tangxifan 1d78725d4d add installation 2019-11-01 17:48:17 -06:00
tangxifan 9a37b66d53 move installation to a script 2019-11-01 17:39:30 -06:00
tangxifan 161664f253 try to comfort iverilog package extraction 2019-11-01 17:24:06 -06:00
tangxifan 2dc3a4eb1f fixing bugs in iVerilog installation 2019-11-01 17:03:21 -06:00
tangxifan 5332588e82 retrying travis installation of iVerilog 10.3 2019-11-01 16:36:29 -06:00
tangxifan 3ae841b80f start refactoring auto-check top testbench generation 2019-11-01 16:33:12 -06:00
tangxifan b61b81b8d8 tuning iverilog version display 2019-11-01 15:29:08 -06:00
tangxifan d4fedb76d7 revert to default iverilog of Ubuntu 18.04 2019-11-01 15:24:58 -06:00