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add debugging mode to see why travis failed

This commit is contained in:
tangxifan 2019-11-01 23:26:08 -06:00
parent 495000c649
commit 5bae8fecde
1 changed files with 5 additions and 5 deletions
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.travis/script.sh
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@ -19,19 +19,19 @@ end_section "OpenFPGA.build"
start_section "OpenFPGA.TaskTun" "${GREEN}..Running_Regression..${NC}"
cd -
echo -e "Testing single-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py single_mode
python3 openfpga_flow/scripts/run_fpga_task.py single_mode --debug --show_thread_logs
#python3 openfpga_flow/scripts/run_fpga_task.py s298
echo -e "Testing multi-mode architectures";
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4
python3 openfpga_flow/scripts/run_fpga_task.py blif_vpr_flow --maxthreads 4 --debug --show_thread_logs
echo -e "Testing compact routing techniques";
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing
python3 openfpga_flow/scripts/run_fpga_task.py compact_routing --debug --show_thread_logs
echo -e "Testing tileable architectures";
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing
python3 openfpga_flow/scripts/run_fpga_task.py tileable_routing --debug --show_thread_logs
echo -e "Testing Verilog generation with explicit port mapping ";
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog
python3 openfpga_flow/scripts/run_fpga_task.py explicit_verilog --debug --show_thread_logs
end_section "OpenFPGA.TaskTun"