AurelienUoU
|
3d079c9421
|
Add folder creation in tuto_fpga_flow.sh to ease the use
|
2019-07-16 07:20:21 -06:00 |
|
AurelienUoU
|
b810b5cab9
|
fpga_flow bug fix + upload k8 architecture
|
2019-07-16 07:04:45 -06:00 |
|
AurelienUoU
|
35e1962732
|
Merge branch 'dev' into documentation
|
2019-07-15 21:19:26 -06:00 |
|
AurelienUoU
|
1cf4e78502
|
Update documentation and help
|
2019-07-15 21:16:15 -06:00 |
tangxifan
|
bcc6346533
|
speeding up identifying unique modules in routing
|
2019-07-14 13:49:20 -06:00 |
|
tangxifan
|
4c6e245885
|
speed-up the unique routing process
|
2019-07-14 12:22:00 -06:00 |
|
tangxifan
|
b690e702f6
|
adding more info to show the progress bar in backannotating GSBs
|
2019-07-13 19:53:44 -06:00 |
|
tangxifan
|
aa4cd850ae
|
try to optimize the runtime of routing uniqueness detection
|
2019-07-13 18:10:34 -06:00 |
|
tangxifan
|
78578f66c5
|
bug fixing for heterogeneous blocks. Still we have bugs in 0-driver CHAN nodes in tileable RRG
|
2019-07-13 14:48:32 -06:00 |
|
AurelienUoU
|
1a5c5ff4a6
|
Update demo simulation result path
|
2019-07-12 16:52:54 -06:00 |
|
AurelienUoU
|
19ccbce9d0
|
Rename option to use circuit_model rather than spice_model
|
2019-07-12 16:18:28 -06:00 |
|
AurelienUoU
|
ef600bc63f
|
Save workspace
|
2019-07-12 15:57:41 -06:00 |
|
AurelienUoU
|
d10cc34c9e
|
Update Readme and tutorial
|
2019-07-12 14:56:08 -06:00 |
Baudouin Chauviere
|
f140e08093
|
Pre-Merge modifications
|
2019-07-12 10:48:43 -06:00 |
|
Baudouin Chauviere
|
a0f1f8d163
|
Fix when explicit verilog is NOT used
|
2019-07-12 10:39:31 -06:00 |
|
tangxifan
|
f0ecc51b51
|
bug fixing to resolve the conflicts between explicit port map and standard cell map
|
2019-07-12 10:38:20 -06:00 |
|
AurelienUoU
|
e65cf9f5fd
|
Update ERI-demo
|
2019-07-12 08:55:19 -06:00 |
|
Baudouin Chauviere
|
40d3460bac
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-11 22:13:30 -06:00 |
|
Baudouin Chauviere
|
29ffa1cdcb
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog
|
2019-07-11 22:13:09 -06:00 |
|
Baudouin Chauviere
|
e461cd0b99
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
|
2019-07-11 22:09:49 -06:00 |
|
Baudouin Chauviere
|
1431ee2f82
|
Fix Explicit verilog
|
2019-07-11 22:09:34 -06:00 |
|
tangxifan
|
cffdebd912
|
bug fixed for the tileable RR graph generator for heterogeneous blocks
|
2019-07-11 21:02:09 -06:00 |
|
tangxifan
|
75ff2e904e
|
Merge branch 'tileable_routing' of https://github.com/LNIS-Projects/OpenFPGA into tileable_routing
|
2019-07-11 19:41:24 -06:00 |
|
tangxifan
|
e633e3d17b
|
update fpga_flow scripts to support vpr_only flow
|
2019-07-11 19:40:58 -06:00 |
|
Baudouin Chauviere
|
c9b84f61c9
|
Hot fix
|
2019-07-11 17:39:02 -06:00 |
|
Baudouin Chauviere
|
d0cd5a2bc1
|
Hot fix
|
2019-07-11 17:27:31 -06:00 |
|
tangxifan
|
9c203ca4d2
|
bug fixing in SDC generator
|
2019-07-11 17:10:08 -06:00 |
|
AurelienUoU
|
1848771e54
|
Add explicit mapping option into fpga_flow
|
2019-07-11 14:44:30 -06:00 |
|
Baudouin Chauviere
|
f4be375637
|
Latest version explicit
|
2019-07-11 14:33:56 -06:00 |
|
AurelienUoU
|
ad0b4b3acd
|
Merge remote-tracking branch 'origin/dev' into documentation
|
2019-07-11 10:15:26 -06:00 |
|
AurelienUoU
|
346b6f3e8e
|
Update docker part in building.md
|
2019-07-11 10:13:55 -06:00 |
|
AurelienUoU
|
c556b85d66
|
Update docker instruction
|
2019-07-11 10:10:30 -06:00 |
|
tangxifan
|
31749fe62b
|
fix bugs in fpga_flow.pl
|
2019-07-10 21:12:00 -06:00 |
|
AurelienUoU
|
3cd214ada2
|
tuto flow v2.1
|
2019-07-10 16:14:38 -06:00 |
|
AurelienUoU
|
db9c4be963
|
Tuto flow v2
|
2019-07-10 16:00:22 -06:00 |
|
AurelienUoU
|
9d7ae2f6ec
|
Update tutorial flow demo draft 6
|
2019-07-10 15:42:31 -06:00 |
|
tangxifan
|
a90316e9f4
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-10 15:13:46 -06:00 |
|
tangxifan
|
acee0161c7
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 15:13:24 -06:00 |
|
tangxifan
|
206fc84a0e
|
minor fix in fpga_flow
|
2019-07-10 15:12:51 -06:00 |
|
AurelienUoU
|
a47711203c
|
Tuto update draft 5
|
2019-07-10 14:59:03 -06:00 |
|
Baudouin Chauviere
|
6441f2ebe7
|
Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev
|
2019-07-10 14:16:55 -06:00 |
|
Baudouin Chauviere
|
0a978db866
|
Fix regression test
|
2019-07-10 14:16:34 -06:00 |
|
tangxifan
|
b7f9831bd2
|
add statistics for unique GSBs
|
2019-07-10 13:08:03 -06:00 |
|
AurelienUoU
|
422ede7610
|
Update tutorial draft 4
|
2019-07-10 12:17:07 -06:00 |
|
tangxifan
|
c6a4d29ed8
|
Merge branch 'tileable_routing' into dev
|
2019-07-10 12:05:43 -06:00 |
|
AurelienUoU
|
cb782a0e9f
|
Draft 3
|
2019-07-10 11:00:36 -06:00 |
|
AurelienUoU
|
905293820f
|
Draft2
|
2019-07-10 10:37:05 -06:00 |
|
AurelienUoU
|
20ce020eb6
|
Tutorial rewrite draft 1
|
2019-07-10 10:03:30 -06:00 |
|
tangxifan
|
57ae5dbbec
|
bug fixing for rectangle FPGA sizes
|
2019-07-09 20:47:52 -06:00 |
|
tangxifan
|
edfe3144c3
|
update profiling, found where runtime is lost
|
2019-07-09 20:28:01 -06:00 |