Commit Graph

784 Commits

Author SHA1 Message Date
Xifan Tang a80199057d logo placement 2019-07-17 18:43:17 -04:00
Xifan Tang 37abd8af40 try to place inline logo 2019-07-17 18:40:26 -04:00
Xifan Tang f3ed949c4b retry placing images 2019-07-17 18:36:49 -04:00
Xifan Tang b104de0263 resize logo again 2019-07-17 17:56:06 -04:00
Xifan Tang b850610cea resize logo to fit 2019-07-17 17:55:10 -04:00
Xifan Tang 17308621bd resize logo on README 2019-07-17 17:53:36 -04:00
Xifan Tang af335dff66 Merge branch 'documentation' of https://github.com/LNIS-Projects/OpenFPGA into documentation 2019-07-17 17:51:45 -04:00
Xifan Tang afd78604c9 Merge branch 'dev' into documentation: resolved conflicts and add logo files 2019-07-17 17:50:11 -04:00
Xifan Tang 6af0d277a2 hot fix on fpga logo 2019-07-17 17:48:01 -04:00
Xifan Tang 5bec11bd6e try to add logo 2019-07-17 17:46:25 -04:00
Xifan Tang e7b40f06b0 Add documentation for fracturable LUTs 2019-07-17 15:21:07 -04:00
tangxifan 8a92a3b589
Merge pull request #19 from LNIS-Projects/egiacomin-patch-5
Update how2use.md
2019-07-17 14:34:23 -04:00
egiacomin 922e40131f
Update how2use.md 2019-07-17 12:33:15 -06:00
tangxifan a16dae6d8c
Merge pull request #18 from LNIS-Projects/egiacomin-patch-4
Egiacomin patch 4
2019-07-17 14:33:12 -04:00
AurelienUoU 5947818761 Typo correction 2019-07-17 12:23:06 -06:00
egiacomin 1da04b9c3a
Update tutorial_index.md 2019-07-17 12:19:57 -06:00
egiacomin 95b56f31d7
Update README.md 2019-07-17 12:11:38 -06:00
egiacomin f10bce826a
Update README.md 2019-07-17 12:07:40 -06:00
egiacomin 77e1480a4c
Merge pull request #14 from LNIS-Projects/dev
Dev - Critical bug fixing and add support for MUX2 standard cell mapping
2019-07-17 11:55:52 -06:00
tangxifan 32e3a556b9 bug fixing herited from explicit mapping 2019-07-17 09:26:05 -06:00
tangxifan 8b8e18a8de bug fixing for mux subckt names 2019-07-17 08:59:57 -06:00
tangxifan a2505ff16a turn on std cell explicit port map 2019-07-17 08:36:09 -06:00
tangxifan dcc96bf7f5 bug fixing 2019-07-17 08:25:52 -06:00
tangxifan 6e1d49d74e start to support direct mapping to MUX2 standard cells 2019-07-17 07:54:23 -06:00
AurelienUoU 8b7f20f1ba Merge branch 'dev' into documentation 2019-07-17 07:33:30 -06:00
AurelienUoU 5b8eaab93f Docker test 2.3 2019-07-16 20:13:46 -06:00
tangxifan 4672311aae
Merge pull request #13 from LNIS-Projects/dev
Dev
2019-07-16 22:10:04 -04:00
AurelienUoU ca2c840e1e Docker test 2.2 2019-07-16 20:04:04 -06:00
AurelienUoU b31fb0ab83 Docker test 2.1 2019-07-16 19:56:13 -06:00
AurelienUoU 31e6ee3ee1 Docker test 2 2019-07-16 19:47:53 -06:00
AurelienUoU 1822e2059a Docker building test 2019-07-16 19:32:06 -06:00
AurelienAlacchi 3aa0a4a5e6
Merge pull request #12 from LNIS-Projects/tangxifan-patch-1
Update building.md
2019-07-16 21:20:38 -04:00
tangxifan d6dfc29508 Now we use the ace from VTR 2019-07-16 17:00:09 -06:00
AurelienUoU 938f2ec68c Update Dockerfile 2019-07-16 16:30:00 -06:00
tangxifan 61026dc623
Update building.md 2019-07-16 16:58:11 -04:00
tangxifan 954a8c14f7 remove redundant files 2019-07-16 14:55:04 -06:00
tangxifan da8745b163
Update README.md 2019-07-16 16:51:52 -04:00
tangxifan 0c68642aad
Update README.md 2019-07-16 16:49:15 -04:00
tangxifan e9154b1f74 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 14:42:45 -06:00
tangxifan b807fdb38a Merge branch 'tileable_routing' into dev 2019-07-16 14:38:18 -06:00
tangxifan be255edc68 now use vtr_assert in ace 2019-07-16 14:37:19 -06:00
Baudouin Chauviere 712eccfa30 Merge branch 'dev', remote-tracking branch 'origin' into explicit_verilog 2019-07-16 13:37:52 -06:00
Baudouin Chauviere 65122d04b3 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 13:37:21 -06:00
tangxifan 115411941b Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into dev 2019-07-16 13:15:45 -06:00
AurelienUoU 509c1d2c80 Link path correction 2019-07-16 13:13:58 -06:00
Baudouin Chauviere 69014704ef Explicit verilog final push 2019-07-16 13:13:30 -06:00
AurelienAlacchi b0017cdbdf
Merge pull request #11 from LNIS-Projects/dev
Dev
2019-07-16 13:08:24 -06:00
Baudouin Chauviere e602006a07 Merge branch 'dev' of https://github.com/LNIS-Projects/OpenFPGA into explicit_verilog 2019-07-16 12:45:13 -06:00
AurelienUoU fe218fc207 Tutorial update 2019-07-16 11:52:24 -06:00
AurelienUoU a04555419a Typo fix 2019-07-16 07:30:25 -06:00