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AurelienUoU 2019-07-16 20:04:04 -06:00
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Dockerfile
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@ -9,7 +9,7 @@ RUN git clone https://github.com/LNIS-Projects/OpenFPGA.git
RUN cd OpenFPGA
RUN echo "mkdir -p build && build" >> build.sh
RUN echo "mkdir -p build && cd build" >> build.sh
RUN echo "cmake .. -DCMAKE_BUILD_TYPE=debug" >> build.sh
RUN echo "make" >> build.sh
RUN chmod +x build.sh

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README.md
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@ -9,7 +9,6 @@ The OpenFPGA framework is the **first open-source FPGA IP generator** supporting
## Compilation
The different ways of compiling can be found in the [**./compilation**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/compilation) folder.<br />
Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md).
**Compilation steps:**

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compilation/dependencies.md
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Yosys
=========
*Information taken from Yosys' GitHub*
You need a C++ compiler with C++11 support (up-to-date CLANG or GCC is recommended) and some standard tools such as GNU Flex, GNU Bison, and GNU Make. TCL, readline and libffi are optional (see ENABLE_* settings in Makefile). Xdot (graphviz) is used by the show command in yosys to display schematics.
ABC
=========
ABC depends on gcc-4.9. It is precisely this version which is required. If another gcc is used, the compilation will not be finished correctly.
ACE2
=========
ACE2 only needs a compiler to work. Gcc is the one chosen in this case. No issue was ever reported with ACE2 so if you have one, raise an issue so that we can modify it here.

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compilation/macos_compilation.md
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MacOS compilation
==================
*This tutorial has been tested under MacOS High Sierra 10.13.4*
Clone the [OpenFPGA git repository:](https://github.com/LNIS-Projects/OpenFPGA)
`git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA.git `
[//todo]: # (There is a submodule in the repository so move to the OpenFPGA directory and clone that too:)
[//]: # (`git submodule init`)
[//todo]: # (`git submodule update`)
Go to the `VPR` directory and build the tool:
`cd ./OpenFPGA/vpr7_x2p/vpr/`
Note: the graphical interface might not be usable since it requires the X11 library. In this case, open the Makefile and change the line 10 "ENABLE_GRAPHICS = true" to false.
`make `
This will generate vpr and a libvpr.a file.
Enhancements of VPR were made.
In order to see them just type:
`./vpr`
This will show the different options that can be used. Our modifications concern the options starting with fpga_spice and fpga_verilog.
A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
`source ./go_fpga_verilog.sh`
This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

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compilation/red_hat_compilation.md
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Red Hat compilation
==================
*This tutorial has been tested under Red Hat 7.5*
Clone the [OpenFPGA git repository:](https://github.com/LNIS-Projects/OpenFPGA)
`git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA.git `
[//todo]: # (There is a submodule in the repository so move to the OpenFPGA directory and clone that too:)
[//]: # (`git submodule init`)
[//todo]: # (`git submodule update`)
Go to the `VPR` directory and build the tool:
`cd ./OpenFPGA/vpr7_x2p/vpr/`
Note: the graphical interface might not be usable since it requires the X11 library. In this case, open the Makefile and change the line 10 "ENABLE_GRAPHICS = true" to false.
`make `
This will generate vpr and a libvpr.a file.
Enhancements of VPR were made.
In order to see them just type:
`./vpr`
This will show the different options that can be used. Our modifications concern the options starting with fpga_spice and fpga_verilog.
A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
`source ./go_fpga_verilog.sh`
This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.

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compilation/ubuntu_compilation.md
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Ubuntu compilation
==================
*This tutorial has been tested under Ubuntu 18.04*
Clone the [OpenFPGA git repository:](https://github.com/LNIS-Projects/OpenFPGA)
`git clone --recurse-submodules https://github.com/LNIS-Projects/OpenFPGA.git `
[//todo]: # (There is a submodule in the repository so move to the OpenFPGA directory and clone that too:)
[//]: # (`git submodule init`)
[//todo]: # (`git submodule update`)
Go to the `VPR` directory and build the tool:
`cd ./OpenFPGA/vpr7_x2p/vpr/`
`make `
This will generate vpr and a libvpr.a file.
Enhancements of VPR were made.
In order to see them just type:
`./vpr`
This will show the different options that can be used. Our modifications concern the options starting with fpga_spice and fpga_verilog.
A script is already prepared in the folder to test FPGA-SPICE and FPGA-Verilog
`source ./go_fpga_verilog.sh`
This script uses the enhanced version of vpr with some new options such as --fpga_verilog_print_top_testbench which automatically generates a testbench for the full FPGA and --fpga_verilog_dir which allows us to choose the destination directory for the verilog output we generate.
For more informations on how the new commands work, please visit [OpenFPGA Options FPGA-SPICE](https://openfpga.readthedocs.io/en/latest/fpga_spice/command_line_usage.html).
As a result, we get a new folder, /verilog_test, which contains the verilog code. The name_top.v contains the full FPGA we just created. Three other folders are created, *lb*, *routing* and *sub_modules*. *lb* contains the different CLBs used in the architecture. *routing* contains the different connection blocks, the switch boxes and the wires. *sub_modules* contains the different modules needed in the architecture.