Tutorial update

README.md

@@ -9,8 +9,8 @@ The OpenFPGA framework is the **first open-source FPGA IP generator** supporting
 
 ## Compilation
 
-The different ways of compiling can be found in the [**./compilation**](https://github.com/LNIS-Projects/OpenFPGA/tree/documentation/compilation) folder.<br />
-Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/building.md).
+The different ways of compiling can be found in the [**./compilation**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/compilation) folder.<br />
+Dependancies and help using docker can be found at [**./tutorials/building.md**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/building.md).
 
 **Compilation steps:**
 1. git clone https://github.com/LNIS-Projects/OpenFPGA.git && cd OpenFPGA # *Clone the repository and go into it*
@@ -29,10 +29,8 @@ OpenFPGA's [full documentation](https://openfpga.readthedocs.io/en/master/) incl
 
 ## Tutorial
 
-You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/documentation/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. 
+You can find in the folder [**./tutorials**](https://github.com/LNIS-Projects/OpenFPGA/tree/master/tutorials). This will help you get in touch with the software and test different configurations to see how OpenFPGA reacts to them. 
 
 Through this tutorial users can learn how to use the flow and set the dependancies.<br />
-The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/documentation/tutorials/tutorial_index.md) will
-
-
+The [tutorial index](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/tutorial_index.md) will guide you through trainings and explain folder oraganization as well as referencing tips and used keywords.
 

tutorials/building.md

@@ -41,7 +41,8 @@ OpenFPGA requires all the dependancies listed below:
 ## Docker
 
 If all these dependancies are not installed in your machine you can choose to use a Docker (docker tool need to be installed). To ease customer first experience a Dockerfile is provided in OpenFPGA folder. A container ready to use can be created with the following command:
-- docker run -it --rm -v `pwd`:/localfile/OpenFPGA -w=“/localfile/OpenFPGA” lnis-projects/open_fpga bash
+- docker run lnis/open_fpga:release <br />
+*Warning: This command is for quick testing. If you want to conserve your work you should certainly use other options as "-v".*
 
 Or a container where you can build OpenFPGA yourself can be created with the following commands:
 - docker build . -t open_fpga

tutorials/fpga_flow/how2use.md

@@ -22,7 +22,7 @@ There is 3 important things to see:
 - fpga_flow.pl calls a configuration file through "config_file" variable
 - fpga_flow.pl calls a list of benchmark to implement and test through "bench_txt" variable
 
-## Configuration file
+### Configuration file
 
 In this file paths have to be full path. Relative path could lead to errors.<br />
 The file is organized in 3 parts: 
@@ -64,7 +64,7 @@ vpr_power_tags = PB Types|Routing|Switch Box|Connection Box|Primitives|Interc St
 
 *This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial/tuto.conf*
 
-## Benchmark list
+### Benchmark list
 
 The benchmark folder contains 3 sub-folders:
 * **Blif**: contains .blif and .act of benchmarks
@@ -76,3 +76,21 @@ The benchmark list file can contain as many benchmarks as available in the same
 top_module/*.v,<int_value>; where <int_value> is the number of channel/wire between each block.
 
 *This example file can be found at OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List/tuto_benchmark.txt*
+
+
+## Modifying flow
+Once dependancies are understood, we can modify the flow by changing the architecture and the route channel width.
+
+### Experiment
+
+* cd OPENFPGAPATHKEYWORD/fpga_flow/configs/tutorial
+* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto.conf
+* cd OPENFPGAPATHKEYWORD/fpga_flow/benchmarks/List
+* replace "200" with "300" in tuto_benchmark.txt
+* cd OPENFPGAPATHKEYWORD/fpga_flow
+* replace the architectures "k6_N10_sram_chain_HC_template.xml" and "k6_N10_sram_chain_HC.xml" respectively with "k8_N10_sram_chain_FC_template.xml" and "k8_N10_sram_chain_FC.xml" in tuto_fpga_flow.sh
+* ./tuto_fpga_flow.sh
+
+### Explanation
+
+With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/image/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/image/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. Indeed, if the routing channel is to low, it could be impossible to route a benchmark or the FPGA output can be delayed.