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Merge branch 'dev', remote-tracking branch 'origin' into explicit_verilog

This commit is contained in:
Baudouin Chauviere 2019-07-16 13:37:52 -06:00
parent b0017cdbdf 65122d04b3
commit 712eccfa30
15 changed files with 235 additions and 81 deletions
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2
fpga_flow/arch/template/k6_N10_sram_chain_HC_template.xml
View File

@ -397,7 +397,7 @@
<port type="output" prefix="inpad" size="1"/>
</circuit_model>
<!-- Hard logic definition for heterogenous blocks -->
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="true" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
<circuit_model type="hard_logic" name="adder" prefix="adder" dump_explicit_port_map="false" spice_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/SpiceNetlists/adder.sp" verilog_netlist="OPENFPGAPATHKEYWORD/vpr7_x2p/vpr/VerilogNetlists/adder.v">
<design_technology type="cmos"/>
<input_buffer exist="on" circuit_model_name="INV1X"/>
<output_buffer exist="on" circuit_model_name="INV1X"/>

2
fpga_flow/tuto_fpga_flow.sh
View File

@ -18,7 +18,7 @@ dir_keyword="GENERATED_DIR_KEYWORD"
rm -rf ${pwd_path}/results_OpenPithon
cd ${pwd_path}/arch
mkdir generated # create folder to save rewritten architecture
mkdir -p generated # create folder to save rewritten architecture
cd ${pwd_path}/scripts
# Replace keyword in config and architecture files

2
tutorials/fpga_flow/how2use.md
View File

@ -93,4 +93,4 @@ Once dependancies are understood, we can modify the flow by changing the archite
### Explanation
With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/image/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/image/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. Indeed, if the routing channel is to low, it could be impossible to route a benchmark or the FPGA output can be delayed.
With this last experiment we replace the [**K6 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut6.pdf) with a [**K8 architecture**](https://github.com/LNIS-Projects/OpenFPGA/blob/master/tutorials/images/architectures_schematics/frac_lut8.pdf), which means a 8-inputs fracturable LUT (implemented by LUT6 and LUT4 with 2 shared inputs). This architecture provides more modes for the CLB and the crossbar changed from a half-connected to a fully connected, implying bigger multiplexor between the CLB and LUT inputs. These requirement in term of interconnection will lead to the increase in routing channel width. Indeed, if the routing channel is to low, it could be impossible to route a benchmark or the FPGA output can be delayed.

62
vpr7_x2p/vpr/ARCH/k6_N10_sram_chain_SC_gf130_2x2.xml
View File

@ -273,7 +273,7 @@
<port type="input" prefix="Set" size="1" is_global="true" default_val="0" is_set="true"/>
<port type="input" prefix="Reset" size="1" is_global="true" default_val="1" is_reset="true"/>
<port type="output" prefix="Q" size="1"/>
<port type="clock" prefix="clk" size="1" is_global="true" default_val="0" />
<port type="clock" prefix="CK" size="1" is_global="true" default_val="0" />
</circuit_model>
<circuit_model type="lut" name="frac_lut6" prefix="frac_lut6" dump_structural_verilog="true">
<design_technology type="cmos" fracturable_lut="true"/>
@ -300,7 +300,7 @@
<port type="input" prefix="D" size="1"/>
<port type="output" prefix="Q" size="1"/>
<port type="output" prefix="Qb" size="1"/>
<port type="clock" prefix="prog_clk" size="1" is_global="true" default_val="0" is_prog="true"/>
<port type="clock" prefix="prog_CK" size="1" is_global="true" default_val="0" is_prog="true"/>
</circuit_model>
<circuit_model type="iopad" name="iopad" prefix="iopad" spice_netlist="/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/SpiceNetlists/io.sp" verilog_netlist="/research/ece/lnis/USERS/alacchi/Current_release/OpenFPGA/vpr7_x2p/vpr/VerilogNetlists/io.v">
<design_technology type="cmos"/>
@ -515,7 +515,7 @@
<input name="cin" num_pins="1"/>
<output name="O" num_pins="20" equivalent="false"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="CK" num_pins="1"/>
<!-- Describe fracturable logic element.
Each fracturable logic element has a 6-LUT that can alternatively operate as two 5-LUTs with shared inputs.
@ -526,7 +526,7 @@
<input name="cin" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="CK" num_pins="1"/>
<mode name="fle_phy" disabled_in_packing="true">
<pb_type name="frac_logic" num_pb="1">
@ -571,12 +571,12 @@
<pb_type name="ff_phy" blif_model=".latch" num_pb="2" class="flipflop" circuit_model_name="static_dff">
<input name="D" num_pins="1" port_class="D"/>
<output name="Q" num_pins="1" port_class="Q"/>
<clock name="clk" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff_phy.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="clk"/>
<clock name="CK" num_pins="1" port_class="clock"/>
<T_setup value="66e-12" port="ff_phy.D" clock="CK"/>
<T_clock_to_Q max="124e-12" port="ff_phy.Q" clock="CK"/>
</pb_type>
<interconnect>
<complete name="direct_clk" input="fle.clk" output="ff_phy[1:0].clk"/>
<complete name="direct_CK" input="fle.CK" output="ff_phy[1:0].CK"/>
<direct name="direct_in" input="fle.in[5:0]" output="frac_logic.in[5:0]"/>
<direct name="direct_cin" input="fle.cin" output="frac_logic.cin"/>
<direct name="direct_cout" input="frac_logic.cout" output="fle.cout"/>
@ -595,18 +595,18 @@
<input name="cin" num_pins="1"/>
<output name="out" num_pins="2"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="CK" num_pins="1"/>
<pb_type name="ble5" num_pb="2" idle_mode_name="blut5">
<input name="in" num_pins="5"/>
<input name="cin" num_pins="1"/>
<output name="out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="CK" num_pins="1"/>
<mode name="blut5">
<pb_type name="flut5" num_pb="1">
<input name="in" num_pins="5"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="CK" num_pins="1"/>
<!-- Regular LUT mode -->
<pb_type name="lut5" blif_model=".names" num_pb="1" class="lut" mode_bits="01" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.5">
<input name="in" num_pins="5" port_class="lut_in" physical_mode_pin="in[5:0]"/>
@ -632,16 +632,16 @@
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy">
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<clock name="CK" num_pins="1" port_class="clock" physical_mode_pin="CK"/>
<T_setup value="66e-12" port="ff.D" clock="CK"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="CK"/>
</pb_type>
<interconnect>
<direct name="direct1" input="flut5.in" output="lut5.in"/>
<direct name="direct2" input="lut5.out" output="ff.D">
<pack_pattern name="ble5" in_port="lut5.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="flut5.clk" output="ff.clk"/>
<direct name="direct3" input="flut5.CK" output="ff.CK"/>
<mux name="mux1" input="ff.Q lut5.out" output="flut5.out" spice_model_sram_offset="0">
<delay_constant max="25e-12" in_port="lut5.out" out_port="flut5.out" />
<delay_constant max="45e-12" in_port="ff.Q" out_port="flut5.out" />
@ -650,7 +650,7 @@
</pb_type>
<interconnect>
<direct name="direct1" input="ble5.in" output="flut5.in"/>
<direct name="direct2" input="ble5.clk" output="flut5.clk"/>
<direct name="direct2" input="ble5.CK" output="flut5.CK"/>
<direct name="direct3" input="flut5.out" output="ble5.out"/>
</interconnect>
</mode>
@ -660,7 +660,7 @@
<input name="cin" num_pins="1"/>
<output name="out" num_pins="1"/>
<output name="cout" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="CK" num_pins="1"/>
<!-- Special dual-LUT mode that drives adder only -->
<pb_type name="lut4" blif_model=".names" num_pb="2" class="lut" mode_bits="11" physical_pb_type_name="frac_lut6" physical_pb_type_index_factor="0.25">
<input name="in" num_pins="4" port_class="lut_in" physical_mode_pin="in[4:0]"/>
@ -696,12 +696,12 @@
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy">
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<clock name="CK" num_pins="1" port_class="clock" physical_mode_pin="CK"/>
<T_setup value="66e-12" port="ff.D" clock="CK"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="CK"/>
</pb_type>
<interconnect>
<direct name="clock" input="arithmetic.clk" output="ff.clk"/>
<direct name="clock" input="arithmetic.CK" output="ff.CK"/>
<direct name="lut_in1" input="arithmetic.in[3:0]" output="lut4[0:0].in[3:0]"/>
<direct name="lut_in2" input="arithmetic.in[3:0]" output="lut4[1:1].in[3:0]"/>
<direct name="lut_to_add1" input="lut4[0:0].out" output="adder.a">
@ -732,7 +732,7 @@
<direct name="carry_out" input="arithmetic.cout" output="ble5.cout">
<pack_pattern name="chain" in_port="arithmetic.cout" out_port="ble5.cout"/>
</direct>
<direct name="direct2" input="ble5.clk" output="arithmetic.clk"/>
<direct name="direct2" input="ble5.CK" output="arithmetic.CK"/>
<direct name="direct3" input="arithmetic.out" output="ble5.out"/>
</interconnect>
</mode>
@ -750,13 +750,13 @@
<direct name="carry_link" input="ble5[0:0].cout" output="ble5[1:1].cin">
<pack_pattern name="chain" in_port="ble5[0:0].cout" out_port="ble5[1:1].cout"/>
</direct>
<complete name="complete1" input="lut5inter.clk" output="ble5[1:0].clk"/>
<complete name="complete1" input="lut5inter.CK" output="ble5[1:0].CK"/>
</interconnect>
</pb_type>
<interconnect>
<direct name="direct1" input="fle.in[4:0]" output="lut5inter.in"/>
<direct name="direct2" input="lut5inter.out" output="fle.out"/>
<direct name="direct3" input="fle.clk" output="lut5inter.clk"/>
<direct name="direct3" input="fle.CK" output="lut5inter.CK"/>
<direct name="carry_in" input="fle.cin" output="lut5inter.cin">
<pack_pattern name="chain" in_port="fle.cin" out_port="lut5inter.cin"/>
</direct>
@ -769,7 +769,7 @@
<pb_type name="ble6" num_pb="1">
<input name="in" num_pins="6"/>
<output name="out" num_pins="1"/>
<clock name="clk" num_pins="1"/>
<clock name="CK" num_pins="1"/>
<pb_type name="lut6" blif_model=".names" num_pb="1" class="lut" mode_bits="00" physical_pb_type_name="frac_lut6" spice_model_sram_offset="0">
<input name="in" num_pins="6" port_class="lut_in" physical_mode_pin="in[5:0]"/>
<output name="out" num_pins="1" port_class="lut_out" physical_mode_pin="lut6_out[0]"/>
@ -795,9 +795,9 @@
<pb_type name="ff" blif_model=".latch" num_pb="1" class="flipflop" physical_pb_type_name="ff_phy" physical_pb_type_index_factor="2" physical_pb_type_index_offset="1">
<input name="D" num_pins="1" port_class="D" physical_mode_pin="D"/>
<output name="Q" num_pins="1" port_class="Q" physical_mode_pin="Q"/>
<clock name="clk" num_pins="1" port_class="clock" physical_mode_pin="clk"/>
<T_setup value="66e-12" port="ff.D" clock="clk"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="clk"/>
<clock name="CK" num_pins="1" port_class="clock" physical_mode_pin="CK"/>
<T_setup value="66e-12" port="ff.D" clock="CK"/>
<T_clock_to_Q max="124e-12" port="ff.Q" clock="CK"/>
</pb_type>
<interconnect>
@ -805,7 +805,7 @@
<direct name="direct2" input="lut6.out" output="ff.D">
<pack_pattern name="ble6" in_port="lut6.out" out_port="ff.D"/>
</direct>
<direct name="direct3" input="ble6.clk" output="ff.clk"/>
<direct name="direct3" input="ble6.CK" output="ff.CK"/>
<mux name="mux1" input="ff.Q lut6.out" output="ble6.out">
<delay_constant max="25e-12" in_port="lut6.out" out_port="ble6.out" />
<delay_constant max="45e-12" in_port="ff.Q" out_port="ble6.out" />
@ -815,7 +815,7 @@
<interconnect>
<direct name="direct1" input="fle.in" output="ble6.in"/>
<direct name="direct2" input="ble6.out" output="fle.out[1:1]"/>
<direct name="direct3" input="fle.clk" output="ble6.clk"/>
<direct name="direct3" input="fle.CK" output="ble6.CK"/>
</interconnect>
</mode> <!-- n1_lut6 -->
</pb_type>
@ -833,7 +833,7 @@
<delay_constant max="95e-12" in_port="clb.I" out_port="fle[9:0].in" />
<delay_constant max="75e-12" in_port="fle[9:0].out" out_port="fle[9:0].in" />
</complete>
<complete name="clks" input="clb.clk" output="fle[9:0].clk">
<complete name="CKs" input="clb.CK" output="fle[9:0].CK">
</complete>
<!-- This way of specifying direct connection to clb outputs is important because this architecture uses automatic spreading of opins.

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_compact_netlist.c
View File

@ -1340,7 +1340,8 @@ void dump_compact_verilog_top_netlist(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_clb2clb_directs(fp, num_clb2clb_directs, clb2clb_direct);
/* Dump configuration circuits */
dump_verilog_configuration_circuits(cur_sram_orgz_info, fp);
dump_verilog_configuration_circuits(cur_sram_orgz_info, fp,
is_explicit_mapping);
/* verilog ends*/
fprintf(fp, "endmodule\n");

62
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_pbtypes.c
View File

@ -370,7 +370,7 @@ void dump_verilog_pb_type_one_bus_port(FILE* fp,
port_prefix, pb_type_port->name);
} else {
if (TRUE == dump_explicit_port_map) {
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
pb_type_port->spice_model_port->lib_name);
}
if (1 < pb_type_port->num_pins) {
@ -1072,6 +1072,10 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
char* mem_subckt_name = NULL;
char* hierarchical_name = NULL;
char* mux_name = NULL;
int num_input_port;
int num_output_port;
t_spice_model_port** input_port;
t_spice_model_port** output_port;
/* Check the file handler*/
if (NULL == fp) {
@ -1087,6 +1091,8 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fan_in = 0;
cur_interc = NULL;
find_interc_fan_in_des_pb_graph_pin(des_pb_graph_pin, cur_mode, &cur_interc, &fan_in);
input_port = find_spice_model_ports(cur_interc->spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
output_port = find_spice_model_ports(cur_interc->spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
if ((NULL == cur_interc)||(0 == fan_in)) {
/* No interconnection matched */
/* Connect this pin to GND for better convergence */
@ -1136,7 +1142,7 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s_%d_ (", cur_interc->spice_model->prefix, cur_interc->spice_model->cnt);
cur_interc->spice_model->cnt++; /* Stats the number of spice_model used*/
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Print the pin names! Input and output
@ -1147,11 +1153,26 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
/* Make sure correctness*/
assert(src_pb_type == des_pb_graph_pin->input_edges[iedge]->input_pins[0]->port->parent_pb_type);
/* Print */
fprintf(fp, "%s__%s_%d_, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
input_port[0]->prefix);
}
fprintf(fp, "%s__%s_%d_",
src_pin_prefix, src_pb_graph_pin->port->name, src_pb_graph_pin->pin_number);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Output */
fprintf(fp, "%s__%s_%d_ ",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
output_port[0]->prefix);
}
fprintf(fp, "%s__%s_%d_",
des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
/* Middle output for wires in logic blocks: TODO: Abolish to save simulation time */
/* fprintf(fp, "gidle_mid_out "); */
/* Local vdd and gnd, TODO: we should have an independent VDD for all local interconnections*/
@ -1257,19 +1278,35 @@ void dump_verilog_pb_graph_pin_interc(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, "%s_size%d ", cur_interc->spice_model->name, fan_in);
fprintf(fp, "%s_size%d_%d_ (", cur_interc->spice_model->prefix, fan_in, cur_interc->spice_model->cnt);
/* Dump global ports */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, FALSE)) {
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_interc->spice_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {
fprintf(fp, ",\n");
}
/* Inputs */
fprintf(fp, "in_bus_%s_size%d_%d_, ",
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
input_port[0]->prefix);
}
fprintf(fp, "in_bus_%s_size%d_%d_",
cur_interc->spice_model->name, fan_in, cur_interc->spice_model->cnt);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Generate the pin_prefix for src_pb_graph_node and des_pb_graph_node*/
if (true == is_explicit_mapping) {
fprintf(fp, ".%s(",
output_port[0]->prefix);
}
generate_verilog_src_des_pb_graph_pin_prefix(src_pb_graph_pin, des_pb_graph_pin, pin2pin_interc_type,
cur_interc, formatted_parent_pin_prefix, &src_pin_prefix, &des_pin_prefix);
des_pin_prefix = chomp_verilog_prefix(des_pin_prefix);
/* Outputs */
fprintf(fp, "%s__%s_%d_, ",
fprintf(fp, "%s__%s_%d_",
des_pin_prefix, des_pb_graph_pin->port->name, des_pb_graph_pin->pin_number);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ", ");
/* Different design technology requires different configuration bus! */
dump_verilog_mux_config_bus_ports(fp, cur_interc->spice_model, cur_sram_orgz_info,
@ -1853,13 +1890,8 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Print inputs, outputs, inouts, clocks
* NO SRAMs !!! They have already been fixed in the bottom level
*/
bool is_explicit_full_name = true;
if (NULL != cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model){
/*if (SPICE_MODEL_HARDLOGIC == cur_pb_type->modes[mode_index].pb_type_children[ipb].spice_model->type){
is_explicit_full_name = false;
}TEST*/
}
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), is_explicit_full_name);
//}
dump_verilog_pb_type_ports(fp, child_pb_type_prefix, 0, &(cur_pb_type->modes[mode_index].pb_type_children[ipb]), FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping), true);
/* Print I/O pads */
dump_verilog_grid_common_port(fp, iopad_verilog_model,
gio_inout_prefix,
@ -1906,7 +1938,7 @@ void dump_verilog_phy_pb_graph_node_rec(t_sram_orgz_info* cur_sram_orgz_info,
/* Print interconnections, set is_idle as TRUE*/
dump_verilog_pb_graph_interc(cur_sram_orgz_info, fp, subckt_name,
cur_pb_graph_node, mode_index,
false);
is_explicit_mapping);
/* Check each pins of pb_graph_node */
/* Check and update stamped_sram_cnt */
/* Now we only dump one Verilog for each pb_type, and instance them when num_pb > 1

21
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_primitives.c
View File

@ -184,7 +184,6 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
dump_verilog_sram_config_bus_internal_wires(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1);
}
if (0 < num_sram_port) {
switch (cur_sram_orgz_info->type) {
case SPICE_SRAM_MEMORY_BANK:
@ -234,6 +233,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* Only dump the global ports belonging to a spice_model
* Disable recursive here !
*/
/*if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, my_bool_to_boolean(is_explicit_mapping))) {*/
if (0 < rec_dump_verilog_spice_model_global_ports(fp, verilog_model, FALSE, FALSE, subckt_require_explicit_port_map)) {
fprintf(fp, ",\n");
}
@ -243,20 +243,23 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
/* print ports --> input ports */
dump_verilog_pb_type_bus_ports(fp, port_prefix, 1, prim_pb_type, FALSE, FALSE,
subckt_require_explicit_port_map);
/* my_bool_to_boolean(is_explicit_mapping));*/
/* IOPADs requires a specical port to output */
if (SPICE_MODEL_IOPAD == verilog_model->type) {
fprintf(fp, ",\n");
assert(1 == num_pad_port);
assert(NULL != pad_ports[0]);
/* Add explicit port mapping if required */
if (TRUE == subckt_require_explicit_port_map) {
fprintf(fp, ".%s(",
if (TRUE == subckt_require_explicit_port_map) {
/*if (true == is_explicit_mapping) {*/
fprintf(fp, ".%s (",
pad_ports[0]->lib_name);
}
/* Print inout port */
fprintf(fp, "%s%s[%d]", gio_inout_prefix,
verilog_model->prefix, verilog_model->cnt);
if (TRUE == subckt_require_explicit_port_map) {
if (TRUE == subckt_require_explicit_port_map) {
/*if (true == is_explicit_mapping) {*/
fprintf(fp, ")");
}
fprintf(fp, ", ");
@ -273,7 +276,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->lib_name);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
@ -294,14 +297,14 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->inv_prefix);
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info,
cur_num_sram, cur_num_sram + num_sram - 1,
1, VERILOG_PORT_CONKT);
if ( (0 < num_sram)
&& (TRUE == verilog_model->dump_explicit_port_map || is_explicit_mapping)) {
&& (TRUE == subckt_require_explicit_port_map)) {
fprintf(fp, ")");
}
break;
@ -311,7 +314,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->lib_name);
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,
@ -331,7 +334,7 @@ void dump_verilog_pb_generic_primitive(t_sram_orgz_info* cur_sram_orgz_info,
&& (TRUE == subckt_require_explicit_port_map)) {
assert( 1 == num_sram_port);
assert( NULL != sram_ports[0]);
fprintf(fp, ".%s(",
fprintf(fp, ".%s (",
sram_ports[0]->inv_prefix);
}
dump_verilog_sram_one_outport(fp, cur_sram_orgz_info,

72
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_report_timing.c
View File

@ -2740,6 +2740,9 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
vpr_printf(TIO_MESSAGE_INFO,
"Generating TCL script to report timing for routing wires\n");
vpr_printf(TIO_MESSAGE_INFO,
"Generating TCL script to report timing for routing wires horizontal\n");
/* Start with horizontal SBs*/
/* We start from a SB[x][y] */
DeviceCoordinator sb_range = device_rr_gsb.get_gsb_range();
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
@ -2759,6 +2762,9 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
if (1 == rr_sb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) {
continue;
}
if (CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) {
continue;
}
/* Check if L_wire exists in the linked list */
L_wire = get_rr_node_wire_length(rr_sb.get_chan_node(side_manager.get_side(), itrack));
/* Get counter */
@ -2793,6 +2799,72 @@ void verilog_generate_routing_wire_report_timing(t_trpt_opts trpt_opts,
}
}
/* close file*/
fclose_wire_L_file_handler_in_llist(rr_path_cnt);
/* Need to reset the different variables */
rr_path_cnt = NULL;
wireL_cnt = NULL;
path_cnt = 0;
vpr_printf(TIO_MESSAGE_INFO,
"Generating TCL script to report timing for routing wires vertical\n");
/* Continue with vertical SBs*/
/* We start from a SB[x][y] */
for (size_t ix = 0; ix < sb_range.get_x(); ++ix) {
for (size_t iy = 0; iy < sb_range.get_y(); ++iy) {
const RRGSB& rr_sb = device_rr_gsb.get_gsb(ix, iy);
for (size_t side = 0; side < rr_sb.get_num_sides(); ++side) {
Side side_manager(side);
for (size_t itrack = 0; itrack < rr_sb.get_chan_width(side_manager.get_side()); ++itrack) {
assert((CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type)
||(CHANY == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type));
/* We only care the output port and it should indicate a SB mux */
if ( (OUT_PORT != rr_sb.get_chan_node_direction(side_manager.get_side(), itrack))
|| (false != rr_sb.is_sb_node_passing_wire(side_manager.get_side(), itrack))) {
continue;
}
/* Bypass if we have only 1 driving node */
if (1 == rr_sb.get_chan_node(side_manager.get_side(), itrack)->num_drive_rr_nodes) {
continue;
}
if (CHANX == rr_sb.get_chan_node(side_manager.get_side(), itrack)->type) {
continue;
}
/* Check if L_wire exists in the linked list */
L_wire = get_rr_node_wire_length(rr_sb.get_chan_node(side_manager.get_side(), itrack));
/* Get counter */
rr_path_cnt = get_wire_L_counter_in_llist(rr_path_cnt, trpt_opts, "vertical", L_wire, &wireL_cnt);
path_cnt = wireL_cnt->cnt;
fp = wireL_cnt->file_handler;
/* This is a new L-wire, create the file handler and the mkdir command to the TCL script */
if (0 == path_cnt) {
fprintf(fp, "exec mkdir -p %s\n",
gen_verilog_one_routing_report_timing_Lwire_dir_path(fpga_verilog_opts.report_timing_path, L_wire));
}
/* Restore the disable_timing for the SB outputs on the path */
/*fprintf(fp, "# Restore disable timing for the following Switch Block output:\n");
restore_disable_timing_one_sb_output(fp,
rr_sb,
rr_sb.get_chan_node(side_manager.get_side(), itrack));*/
fprintf(fp, "# Report timing for all the paths using this output:\n");
/* Dump report_timing command */
verilog_generate_one_routing_segmental_report_timing(fp, fpga_verilog_opts,
rr_sb,
side_manager.get_side(), itrack,
LL_rr_node, "vertical", &path_cnt);
/* Disable the timing again */
/*fprintf(fp, "# Set disable timing for the following Switch Block output:\n");
set_disable_timing_one_sb_output(fp,
rr_sb,
rr_sb.get_chan_node(side_manager.get_side(), itrack));*/
/* Update the wire L*/
update_wire_L_counter_in_llist(rr_path_cnt, L_wire, path_cnt);
}
}
}
}
/* close file*/
fclose_wire_L_file_handler_in_llist(rr_path_cnt);

9
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_routing.c
View File

@ -981,6 +981,7 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
int cur_bl, cur_wl;
t_spice_model* mem_model = NULL;
char* mem_subckt_name = NULL;
int num_input_port, num_output_port, num_sram_port;
/* Check the file handler*/
if (NULL == fp) {
@ -1096,8 +1097,11 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
fprintf(fp, ",\n");
}
t_spice_model_port** input_port = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
t_spice_model_port** output_port = find_spice_model_ports(verilog_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".in(");
fprintf(fp, ".%s(",
input_port[0]->prefix);
fprintf(fp, "%s_size%d_%d_inbus), ",
verilog_model->prefix, mux_size, verilog_model->cnt);
}
@ -1107,7 +1111,8 @@ void dump_verilog_unique_switch_box_mux(t_sram_orgz_info* cur_sram_orgz_info,
}
/* Output port */
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".out(");
fprintf(fp, ".%s(",
output_port[0]->prefix);
dump_verilog_unique_switch_box_chan_port(fp, rr_sb, chan_side, cur_rr_node, OUT_PORT);
fprintf(fp, ")");
}

5
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_sdc.c
View File

@ -2732,12 +2732,13 @@ void verilog_generate_sdc_pnr(t_sram_orgz_info* cur_sram_orgz_info,
}
/* Part 5. Output routing constraints for Connection Blocks */
if (TRUE == sdc_opts.constrain_routing_channels) {
/* BC: Might not be useful as it constrains nets which are assigned too*/
/*if (TRUE == sdc_opts.constrain_routing_channels) {
verilog_generate_sdc_constrain_routing_channels(sdc_opts, arch,
LL_nx, LL_ny,
LL_num_rr_nodes, LL_rr_node,
LL_rr_node_indices, LL_rr_indexed_data);
}
}*/
/* Part 6. Output routing constraints for Programmable blocks */
if (TRUE == sdc_opts.constrain_pbs) {

10
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_submodules.c
View File

@ -722,8 +722,10 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp,
t_spice_model* tgate_spice_model = cur_spice_model->pass_gate_logic->spice_model;
int num_input_port = 0;
int num_output_port = 0;
int num_sram_port = 0;
t_spice_model_port** input_port = NULL;
t_spice_model_port** output_port = NULL;
t_spice_model_port** sram_port = NULL;
assert(TRUE == cur_spice_model->dump_structural_verilog);
@ -737,6 +739,7 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp,
assert ( NULL != tgate_spice_model);
input_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_INPUT, &num_input_port, TRUE);
output_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_OUTPUT, &num_output_port, TRUE);
sram_port = find_spice_model_ports(tgate_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE);
/* Check */
assert ((3 == num_input_port));
@ -764,9 +767,9 @@ void dump_verilog_cmos_mux_one_basis_module_structural(FILE* fp,
fprintf(fp, "input [0:%d] in,\n", num_input_basis_subckt - 1);
fprintf(fp, "output out,\n");
fprintf(fp, "input [0:%d] mem,\n",
num_mem - 1);
num_mem - 1/*, sram_port[0]->prefix*/);
fprintf(fp, "input [0:%d] mem_inv);\n",
num_mem - 1);
num_mem - 1/*, sram_port[0]->prefix*/);
/* Verilog Behavior description for a MUX */
fprintf(fp, "//---- Structure-level description -----\n");
/* Special case: only one memory, switch case is simpler
@ -1678,7 +1681,8 @@ void dump_verilog_cmos_mux_submodule(FILE* fp,
switch (cur_mux_structure) {
case SPICE_MODEL_STRUCTURE_TREE:
dump_verilog_cmos_mux_tree_structure(fp, mux_basis_subckt_name,
spice_model, spice_mux_arch, num_sram_port, sram_port, is_explicit_mapping);
spice_model, spice_mux_arch,
num_sram_port, sram_port, is_explicit_mapping);
break;
case SPICE_MODEL_STRUCTURE_ONELEVEL:
dump_verilog_cmos_mux_onelevel_structure(fp, mux_basis_subckt_name,

33
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.c
View File

@ -1069,7 +1069,8 @@ void dump_verilog_configuration_circuits_standalone_srams(t_sram_orgz_info* cur_
*/
static
void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp,
bool is_explicit_mapping) {
int num_mem_bits = 0;
/* Check */
@ -1088,12 +1089,31 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
verilog_config_peripheral_prefix,
verilog_config_peripheral_prefix);
/* Scan-chain input*/
if (true == is_explicit_mapping) {
fprintf(fp, ".%s (",
top_netlist_scan_chain_head_prefix);
}
dump_verilog_generic_port(fp, VERILOG_PORT_CONKT,
top_netlist_scan_chain_head_prefix, 0, 0);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_in_local_bus (");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, -1, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ",\n");
if (true == is_explicit_mapping) {
fprintf(fp, ".scff_scff_out_local_bus (");
}
dump_verilog_sram_one_local_outport(fp, cur_sram_orgz_info, 0, num_mem_bits - 1, 0, VERILOG_PORT_CONKT);
if (true == is_explicit_mapping) {
fprintf(fp, ")");
}
fprintf(fp, ");\n");
fprintf(fp, "//------ END Configuration peripheral Scan-chain FFs -----\n");
@ -1103,7 +1123,8 @@ void dump_verilog_configuration_circuits_scan_chains(t_sram_orgz_info* cur_sram_
/* Dump a memory bank to configure all the Bit lines and Word lines */
static
void dump_verilog_configuration_circuits_memory_bank(FILE* fp,
t_sram_orgz_info* cur_sram_orgz_info) {
t_sram_orgz_info* cur_sram_orgz_info,
bool is_explicit_mapping) {
int num_bl, num_wl;
int num_reserved_bl, num_reserved_wl;
int num_array_bl, num_array_wl;
@ -1210,16 +1231,18 @@ void dump_verilog_configuration_circuits_memory_bank(FILE* fp,
* 3. Standalone SRAMs
*/
void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp) {
FILE* fp,
bool is_explicit_mapping) {
switch(cur_sram_orgz_info->type) {
case SPICE_SRAM_STANDALONE:
dump_verilog_configuration_circuits_standalone_srams(cur_sram_orgz_info, fp);
break;
case SPICE_SRAM_SCAN_CHAIN:
dump_verilog_configuration_circuits_scan_chains(cur_sram_orgz_info, fp);
dump_verilog_configuration_circuits_scan_chains(cur_sram_orgz_info, fp, is_explicit_mapping);
break;
case SPICE_SRAM_MEMORY_BANK:
dump_verilog_configuration_circuits_memory_bank(fp, cur_sram_orgz_info);
/* BC: TODO explicit_mapping*/
dump_verilog_configuration_circuits_memory_bank(fp, cur_sram_orgz_info, is_explicit_mapping);
break;
default:
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid type of SRAM organization in Verilog Generator!\n",

3
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_top_netlist_utils.h
View File

@ -24,7 +24,8 @@ void dump_verilog_clb2clb_directs(FILE* fp,
int num_directs, t_clb_to_clb_directs* direct);
void dump_verilog_configuration_circuits(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp);
FILE* fp,
bool is_explicit_mapping);
void dump_verilog_top_module_ports(t_sram_orgz_info* cur_sram_orgz_info,
FILE* fp,

25
vpr7_x2p/vpr/SRC/fpga_x2p/verilog/verilog_utils.c
View File

@ -902,8 +902,8 @@ int rec_dump_verilog_spice_model_global_ports(FILE* fp,
/* Add explicit port mapping if required */
if (TRUE == require_explicit_port_map ) {
fprintf(fp, ".%s(",
cur_spice_model_port->lib_name);
/*cur_spice_model_port->prefix);*/
cur_spice_model_port->lib_name);
//cur_spice_model_port->prefix);
}
fprintf(fp, "%s[0:%d]",
cur_spice_model_port->prefix,
@ -2575,6 +2575,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
int num_mux_reserved_conf_bits,
int num_mux_conf_bits,
bool is_explicit_mapping) {
int num_sram_port;
t_spice_model_port** sram_port = find_spice_model_ports(mux_spice_model, SPICE_MODEL_PORT_SRAM, &num_sram_port, TRUE);
/* Check the file handler*/
if (NULL == fp) {
vpr_printf(TIO_MESSAGE_ERROR,"(File:%s,[LINE%d])Invalid file handler.\n",
@ -2595,7 +2597,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
* We do not need a prefix implying MUX name, size and index
*/
if (true == is_explicit_mapping) {
fprintf(fp, ".sram(");
fprintf(fp, ".%s (",
sram_port[0]->prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
@ -2607,7 +2610,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
}
fprintf(fp, ", ");
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram_inv(");
fprintf(fp, ".%s_inv (",
sram_port[0]->prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
@ -2624,7 +2628,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
* We need a prefix implying MUX name, size and index
*/
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram(");
fprintf(fp, ".%s (",
sram_port[0]->prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
@ -2636,7 +2641,8 @@ void dump_verilog_cmos_mux_config_bus_ports(FILE* fp, t_spice_model* mux_spice_m
}
fprintf(fp, ",\n");
if (TRUE == is_explicit_mapping) {
fprintf(fp, ".sram_inv(");
fprintf(fp, ".%s_inv (",
sram_port[0]->prefix);
}
dump_verilog_mux_sram_one_outport(fp, cur_sram_orgz_info,
mux_spice_model, mux_size,
@ -3102,6 +3108,7 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
int num_bl_per_sram = 0;
int num_wl_per_sram = 0;
int iport = 0;
t_llist* spice_model_head = NULL;
/* Check the file handler*/
if (NULL == fp) {
@ -3198,7 +3205,11 @@ void dump_verilog_mem_sram_submodule(FILE* fp,
break;
case SPICE_SRAM_SCAN_CHAIN:
/* Only dump the global ports belonging to a spice_model */
if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, my_bool_to_boolean(is_explicit_mapping))) {
rec_stats_spice_model_global_ports(cur_sram_verilog_model,
TRUE,
&spice_model_head);
if (0 < dump_verilog_global_ports( fp, spice_model_head, FALSE, is_explicit_mapping)) {
//if (0 < rec_dump_verilog_spice_model_global_ports(fp, cur_sram_verilog_model, FALSE, TRUE, FALSE)) {
fprintf(fp, ",\n");
}
if (SPICE_MODEL_MUX == cur_verilog_model->type) {

5
vpr7_x2p/vpr/regression_verilog.sh
View File

@ -25,7 +25,7 @@ arch_ff_keyword="FFPATHKEYWORD"
# Remove previous designs
rm -rf $verilog_output_dirpath/$verilog_output_dirname
mkdir ${OpenFPGA_path}/fpga_flow/arch/generated
mkdir -p ${OpenFPGA_path}/fpga_flow/arch/generated
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $template_arch_xml_file -o $arch_xml_file
@ -33,7 +33,8 @@ perl rewrite_path_in_file.pl -i $arch_xml_file -k $arch_ff_keyword $new_ff_path
cd -
# Run VPR
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy --fpga_verilog_explicit_mapping
#echo "./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping"
./vpr $arch_xml_file $blif_file --full_stats --nodisp --activity_file $act_file --fpga_verilog --fpga_verilog_dir $verilog_output_dirpath/$verilog_output_dirname --fpga_x2p_rename_illegal_port --fpga_bitstream_generator --fpga_verilog_print_top_testbench --fpga_verilog_print_input_blif_testbench --fpga_verilog_include_timing --fpga_verilog_include_signal_init --fpga_verilog_print_formal_verification_top_netlist --fpga_verilog_print_autocheck_top_testbench $verilog_reference --fpga_verilog_print_user_defined_template --route_chan_width $vpr_route_chan_width --fpga_verilog_include_icarus_simulator --fpga_verilog_print_report_timing_tcl --power --tech_properties $tech_file --fpga_verilog_print_sdc_pnr --fpga_verilog_print_sdc_analysis --fpga_x2p_compact_routing_hierarchy #--fpga_verilog_explicit_mapping
cd $fpga_flow_scripts
perl rewrite_path_in_file.pl -i $ff_path -o $new_ff_path -k $ff_keyword $ff_include_path